lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 13

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

Global Reset
Cascade
Control
Output Tri-state
Control
Data Output
Ports
LOGIC Devices Incorporated
REN0 - Read Enable 0
REN0 enables/disables memory read accesses and read pointer auto-incrementing. Data is read from
memory and the read address pointer is incremented on the rising edge of RCLK when REN0 is LOW. An
additional 8 RCLK cycles, with REN0 LOW, are required for the memory contents to appear on Q0[11-0].
REN1 - Read Enable 1
In dual-channel mode, REN1 enables/disables memory read accesses and read pointer auto-increment-
ing. Data is read from memory and the read address pointer is incremented on the rising edge of RCLK
when REN1 was LOW for the previous rising edge of RCLK. An additional 8 RCLK cycles, with REN1
LOW, are required for the memory contents to appear on Q1[11-0]. In single-channel mode, tie REN1
LOW - unless used as an ADDR external address bit (See ADDR descr.).
RESET - Global Reset
Bringing RESET LOW upon power-up ensures that the read/write pointers are cleared and configuration
registers loaded to their default states. An internal power-on reset makes this pin optional. RESET is active
low and will hold all state machines in their clear statess until it is released HIGH. When applying this global
reset, at least one rising edge of both WCLKx and RCLK should capture a LOW on the RESET signal.
CHIP_ADDR6-0 - Chip Address (CA6-0)
CHIP_ADDR6-0 determines the LF4430’s address on the two-wire microprocessor bus. Each LF4430
chip’s 7-bit two-wire serial microprocessor interface address is equal to its CHIP_ADDR6-0.
OE0 - Output Enable 0
When OE0 is LOW, Q0[11-0] is enabled and driven as an output. When OE0 is HIGH, Q0[11-0] is placed
in a high-impedance state. Depending on WIDTH settings, unused Q0/Q1 bits are automatically tristated.
Flag outputs are not affected by OE0.
OE1 - Output Enable 1
With data widths over 12bits, OE1 should be tied to OE0. When OE1 is LOW, Q1[11-0] is enabled and
driven as an output. When OE1 is HIGH, or in any single-channel mode with a data width of 12bits or less,
Q1[11-0] is automatically tristated. Depending on WIDTH settings, unused Q0/Q1 bits are automatically
tristated. Flag outputs are not affected by OE1.
Q0[11-0] / Q1[11-0] - Data Output Port 0/1
Q0/Q1 is a 24-bit registered data output port. Please see Figure 5/6/7 on page 5/6/7 for memory and
I/O organization. For any single-channel configuration, including data widths of 16bits and higher, data
is read from a combined Q0/Q1 output port, with data updated on the rising edge of RCLK when REN0
is LOW. For data widths of 12bits or less, data is read out on Q0[11-0]. For two independent FIFOs,
Q0 services channel 0 and Q1 services channel 1. Depending on WIDTH settings, unused output bits
from Q0/Q1 are automatically tri-stated.
Detailed Signal Definitions
www.logicdevices.com
13
PRELIMINARY
High Performance Memory Product
Video Memory / FIFO
January 23, 2008 LDS-44xx-A
FRAME
MEMORY
LF4460
LF4430
LF4415