lf4415 LOGIC Devices Inc., lf4415 Datasheet - Page 2

• Manufacturer Part Number: lf4415
• Description: Video Memory / Fifo
• Manufacturer: LOGIC Devices Inc.

LOGIC Devices Incorporated
Simple
Configuration
& Control
Memory
Organization
Addressing
Flexibility
LF44xx Functional Block Diagram
D[23:0]
WCLR
WSET
WCLK
WIEN
WEN
LF4430 Overview
Imagine a full-frame HDTV frame buffer solution in a single, tiny chip. Add a simple, easy to use SRAM
interface and complex addressing capability on-chip - and you have a LOGIC Devices HD Frame Memory.
The LF44xx Video Memory family supports all SDTV/HDTV video formats and range from 15 to 60Mbit
densities with configurable memory organizations and parallel word-widths. Independent (asynchronous)
clock domains on the device’s data I/O ports enable synchronization and rate matching. Since reads are
non-destructive, a given data value written into the memory core may be read as many times as desired.
Applications requiring additional depth may cascade devices for depth expansion.
In addition to memory organization flexibility, the LF44xx family simplifies memory addressing tasks. Timing
reference signals (TRS) on an incoming video signal can be detected and used to provide an auto-clear on
the Write pointer/address for simplified frame-sync applications. Write or Read pointers can be forced (in
real-time) to any location within the entire address space using an external 24bit address port. Full-time
Write or Read address manipulation using the external address port enables such applications as image
rotation, Region-of-Interest extraction, or Picture-in-Picture (PIP).
Devices are configured by simply tying off static control pins. If a more complex memory implementation
is required, access to application specific functions/features are provided through 8bit configuration words
programmed via a standard I
MODE control pins define memory organization, I/O word width, and number of unique FIFO channels.
Combinations of MODE settings range from 8 to 24bit I/O in single or dual FIFO configurations.
www.logicdevices.com
24
RDWRB
CONTROL
WRITE
MODE
MODE
4
& CONTROL
ADDRESS
SDA
2
C serial interface.
WRITE
SCL
ADDRESS OVERRIDE
MEMORY ARRAY
60 Mbit (LF4460)
30 Mbit (LF4430)
15 Mbit (LF4415)
I C
2
CHIP_ADDR
ADDR[23:0]
CONTROL
2
24
7
& CONTROL
6-0
ADDRESS
READ
TDI
PRELIMINARY
TDO
JTAG
CONTROL
High Performance Memory Product
TMS
READ
FLAGS
TCK
Video Memory / FIFO
PE0
PF0
COLLIDE0
24
RCLR
RSET
RCLK
REN
MEMORY
FRAME
January 23, 2008 LDS-44xx-A
Q[23:0]
OE
LF4460
LF4430
LF4415