km4132g271a ETC-unknow, km4132g271a Datasheet - Page 16

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
DEVICE OPERATIONS (Continued)
WRITE PER BIT
selectively masks bits of data being written to the devices. The
mask is stored in an internal register and applied to each bit of
data written when enabled. Bank active command with
DSF=High enabled write per bit for associated bank. Bank active
command with DSF=Low disables write per bit for the associ-
ated bank. The mask used for write per bit operations is stored
in the mask register accessed by SWCBR(Special Mode Regis-
ter Set Command). When a mask bit=1, the associated data bit
is written when a write command is executed and write per bit
has been enabled for the bank being written. When a mask
bit=0, the associated data bit is unaltered when a write com-
mand is executed and the write per bit has been enabled for the
bank being written. No additional timing conditions are required
for write per bit operations. Write per bit writes can be either sin-
gle write, burst writes or block writes. DQM masking is the same
for write per bit and non-WPB write.
BLOCK WRITE
consecutive 8 columns of data within a RAM device during a sin-
gle access cycle. During block write the data to be written comes
from an internal "color" register and DQ I/O pins are used for
independent column selection. The block of column to be written
is aligned on 8 column boundaries and is defined by the column
address with the 3 LSB's ignored. Write command with DSF=1
enables block write for the associated bank. A write command
with DSF=0 enables normal write for the associated bank. The
block width is 8 column where column="n" bits for by "n" part.
The color register is the same width as the data port of the
chip.It is written via a SWCBR where data present on the DQ pin
is to be coupled into the internal color register. The color register
provides the data masked by the DQ column select, WPB
mask(If enabled), and DQM byte mask. Column data mask-
ing(Pixel masking) is provided on an individual column basis for
each byte of data. The column mask is driven on the DQ pins
during a block write command. The DQ column mask function is
segmented on a per bit basis(i.e. DQ[0:7] provides the column
mask for data bits[0:7], DQ[8:15] provides the column mask for
data bits[8:15], DQ0 masks column[0] for data bits[0:7], DQ9
masks column [1] for data bits [8:15], etc). Block writes are
always non-burst, independent of the burst length that has been
programmed into the mode register. Back to back block writes
are allowed provided that the specified block write cycle
time(
active command with DSF=1, then write per bit masking of the
color register data is enabled.
If write per bit was disabled by a bank active command with
DSF=0, the write per bit masking of the color register data is dis-
abled. DQM masking provides independent data byte masking
during block write exactly the same as it does during normal
write operations, except that the control is extended to the con-
secutive 8 columns of the block write.
Write per bit(i.e. I/O mask mode) for SGRAM is a function that
Block write is a feature allowing the simultaneous writing of
t
BWC
) is satisfied. If write per bit was enabled by the bank
Timing Diagram to lllustrate
1. 1 CLK Cycle Block Write(
2. 2 CLK Cycle Block Write(
CLOCK
CKE
CS
RAS
CAS
WE
DSF
CLOCK
CKE
CS
RAS
CAS
WE
DSF
0
0
1 CLK BW
2 CLK BW
1
t
HIGH
t
HIGH
1
BWC
BWC
2
Rev.0 (August 1997)
¡Â
>
t
CC
t
CC
CMOS SGRAM
3
)
t
)
BWC
2
4