km4132g271a ETC-unknow, km4132g271a Datasheet - Page 17

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
SUMMARY OF 1M Byte SGRAM BASIC FEATURES AND BENEFITS
Interface
Bank
Page Depth / 1 Row
Total Page Depth
Burst Length(Read)
Burst Length(Write)
Burst Type
CAS Latency
Block Write
Color Register
Mask Register
Mask function
Note : CKE to CLK disable/enable=1 clock
DQ(CL2)
DQ(CL3)
Internal
Features
CMD
CKE
CLK
CLK
1) Clock Suspended During Write (BL=4)
WR
D
D
0
0
D
D
Pixel Mask at Block Write
1
1
128K x 32 x 2 SGRAM
Sequential & Interleave
1, 2, 4, 8 Full Page
1, 2, 4, 8 Full Page
Synchronous
Not Written
Write per bit
1024 bytes
Masked by CKE
8 Columns
DQM
256 bit
BRSW
1 ea.
1 ea.
2 ea
2, 3
D
D
2
2
0-3
D
D
3
3
Better interaction between memory and system without wait-state of
asynchronous DRAM.
High speed vertical and horizontal drawing.
High operating frequency allows performance gain for SCROLL, FILL,
and BitBLT.
Pseudo-infinite row length by on-chip interleaving operation.
Hidden row activation and precharge.
High speed vertical and horizontal drawing.
High speed vertical and horizontal drawing.
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
Programmable burst of 1, 2, ,4, 8 and full page transfer per column
addresses.
Switch to burst length of 1 at write without MRS.
Compatible with Intel and Motorola CPU based system.
Programmable CAS latency.
High speed FILL, CLEAR, Text with color registers.
Maximum 32 byte data transfers(e.g. for 8bpp : 32 pixels) with plane and
byte masking functions.
A and B bank share.
Write-per-bit capability(bit plane masking). A and B banks share.
Byte masking(pixel masking for 8bpp system) for data-out/in
Each bit of the mask register directly controls a corresponding bit plane.
Byte masking(pixel masking for 8bpp system) for color by DQi
2) Clock Suspended During Read (BL=4)
RD
Q
0
Benefits
D
Q
Q
0
1
0
Suspended Dout
Masked by CKE
Rev.0 (August 1997)
Q
Q
2
1
CMOS SGRAM
Q
Q
3
2
Q
3