km4132g271a ETC-unknow, km4132g271a Datasheet - Page 40

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

DQ
CLOCK
KM4132G271A
Burst Read Single bit Write Cycle @Burst Length=2, BRSW
ADDR
DQM
CKE
RAS
CAS
DSF
WE
CS
CL=2
CL=3
A
A
9
8
*Note :
*Note 1
0
Row Active
(A-Bank)
RAa
RAa
1
1. BRSW mode is enabled by setting A
2. When BRSW write command with auto precharge is executed, keep it in mind that
3. WPB function is also possible at BRSW mode.
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programed burst length.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
2
3
(A-Bank)
DAa0
Write
DAa0
CAa
4
Row Active
(B-Bank)
RBb
RBb
Auto Precharge
5
Read with
(A-Bank)
CAb
6
9
7
"High" at MRS (Mode Register Set).
QAb0 QAb1
8
QAb0 QAb1
9
HIGH
10
Row Active
(A-Bank)
RAc
RAc
Auto Precharge
11
Write with
(B-Bank)
DBc0
DBc0
CBc
12
13
*Note 2
(A-Bank)
Read
CAd
t
RAS
14
should not be violated.
Rev.0 (August 1997)
15
QAd0 QAd1
CMOS SGRAM
16
QAd0 QAd1
17
Precharge
(A-Bank)
: Don't care
18
19