km4132g271a ETC-unknow, km4132g271a Datasheet - Page 38

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

DQ
KM4132G271A
CLOCK
Read Interrupted by Precharge Command & Read Burst Stop Cycle (@Full page Only)
ADDR
DQM
DSF
CKE
RAS
CAS
WE
CS
CL=2
CL=3
A
A
9
8
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
0
Row Active
(A-Bank)
RAa
RAa
1
2. About the valid DQ's after burst stop, it is same as the case of RAS interrupt.
3. Burst stop is valid at full page mode.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
2
3
(A-Bank)
*Note 1
Read
CAa
4
5
QAa0 QAa1 QAa2 QAa3 QAa4
6
QAa0 QAa1 QAa2 QAa3 QAa4
7
*Note 2
8
Burst Stop
9
HIGH
10
1
(A-Bank)
*Note 1
Read
CAb
11
2
12
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
13
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
14
Rev.0 (August 1997)
15
CMOS SGRAM
16
Precharge
(A-Bank)
17
: Don't care
18
1
19
2