km4132g271a ETC-unknow, km4132g271a Datasheet - Page 22

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
8. Burst Stop & Precharge Interrupt
9. MRS & SMRS
*Note :
1) Write Interrupted by Precharge (BL=4)
3) Read Interrupted by Precharge (BL=4)
1. t
2. t
3. Number of valid output data after Row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
1) Mode Register Set
DQ(CL3)
DQ(CL2)
MRS can be issued only at all bank precharge state.
RDL
BDL
DQM
CMD
CMD
CLK
CLK
DQ
CMD
: 1 CLK, Last Data in to Row Precharge.
: 1 CLK, Last Data in to Burst Stop Delay.
CLK
WR
RD
D
PRE
0
D
Note 4
1
t
RP
PRE
D
Q
2
0
t
RDL
PRE
D
Q
Q
3
Note 1
MRS ACT
1
0
1CLK
1
Note 3
Q
1
2
2) Special Mode Register Set
2) Write Burst Stop (Full Page Only)
4) Read Burst Stop (Full Page Only)
DQ(CL3)
DQ(CL2)
CMD
CLK
CMD
CMD
CLK
CLK
DQ
SMRS
WR
RD
1CLK
D
0
ACT SMRS SMRS
1CLK
D
1
Rev.0 (August 1997)
STOP
1CLK
D
Q
2
0
t
CMOS SGRAM
BDL
STOP
1CLK
Q
Q
1
0
BW
1
Note 3
Q
1
2