km4132g271a ETC-unknow, km4132g271a Datasheet - Page 21

• Manufacturer Part Number: km4132g271a
• Description: 128k 32bit Banks Synchronous Graphic
• Manufacturer: ETC-unknow

KM4132G271A
5. Write Interrupted by Precharge & DQM
6. Precharge
7. Auto Precharge
*Note :
*Note :
1. To inhibit invalid write, DQM should be issued.
2. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
1) Normal Write (BL=4)
3) Read (BL=4)
1) Normal Write (BL=4)
3) Read (BL=4)
1. t
2. Number of valid output data after Row Precharge : 1, 2 for CAS Latency =2, 3 respectively.
3. The row active command of the precharge bank can be issued after t
DQ(CL2)
DQ(CL3)
DQ(CL2)
DQ(CL3)
interrupt but only another bank precharge of dual banks operation.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
BPL
CMD
CMD
CMD
CMD
CLK
CLK
CLK
CLK
DQ
DQ
: Block write data-in to PRE command delay
DQM
CMD
CLK
DQ
WR
WR
RD
WR
RD
D
D
D
0
0
0
D
D
D
1
1
1
D
D
D
Q
Q
2
2
2
0
0
PRE
D
D
D
Q
Q
Q
Q
Masked by DQM
3
3
3
1
0
1
0
t
Note 1
RDL
Auto Precharge Starts
Auto Precharge Starts
Note 2
Note 1
PRE
PRE
Q
Q
Q
Q
2
1
2
1
Q
Q
Q
Q
Note 3
Note 3
2
2
3
3
1
Note 2
Q
Q
3
3
2
2) Block Write
2) Block Write
(CL 2, 3)
RP
CMD
CMD
CLK
CLK
from this point.
DQ
DQ
Pixel
BW
t
Pixel
BW
BPL
Auto Precharge Starts
t
Note 1
BPL
Rev.0 (August 1997)
Note 3
t
CMOS SGRAM
PRE
BAL
t
RP