lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 10

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
Parallel MPU
Interface
LOGIC Devices Incorporated
Device Configuration
There are four operations that can be performed between the master and the slave. They are: Write to
consecutive registers, write to a single control register, read from consecutive registers and read from a
single register. To write to consecutive control registers, a start signal and base address must be sent
with the R/W bit as described above. After the acknowledgment back from the appropriate slave, the
8-bit address of the target control register must be written to the slave with the R/W bit LOW. The slave
then acknowledges by setting SDA LOW. The data byte to be written into the register can now be
transferred on SDA. The slave then acknowledges by pulling SDA LOW on the next positive going pulse
of SCL. The first control register address loaded into the LF3312 is considered as the beginning address
for consecutive writes, and automatically increments to the next higher address space. Therefore after the
acknowledgement, the data byte to configure register (first address + 1) can now be transferred from master
to slave. At any point a stop signal can be given to end the data transfer. To write to a single control register,
the same technique can be applied adding a stop signal after the first data write.
To read from consecutive control registers, the master must again give the start signal followed by a
base address with the R/W bit = 0, as if the master wants to write to the slave. The appropriate slave
then acknowledges. The master will then transfer the target register address to the slave and wait for
an acknowledge. The master will then give a repeated start signal to the slave, along with the base
address and R/W bit this time HIGH signifying a read and wait for an acknowledge. The user must write
to the LF3312 to select the appropriate initial target register. Otherwise the starting position of the read is
uncertain. Once the LF3312 acknowledges, the next byte of data on SDA is the contents of the addressed
register sent from the device. If the master acknowledges, the LF3312 will send the next higher register’s
contents on the following byte of data. To read from only one register is the same procedure as for
consecutive reading with a stop signal following the transfer of the register’s contents.
The parallel MPU interface can be used to write instructions to the control registers or to read them back for
verification. When the PROGRAM pin is HIGH, the parallel interface is selected. An external processor can
write into an internal register by setting PADDR to the desired register address, selecting the chip using the
CSB pin, setting PDATA to the desired value and then pulsing WEB LOW. The data will be written into the
selected register when both WEB and CSB are LOW, and will be held when either signal goes HIGH. To
read from a control register the processor must set PADDR to the desired address, select the chip with the
CSB pin, and then set REB LOW. The chip will then drive PDATA with the contents of the selected register.
After the processor has read the value from PDATA, REB and CSB should be set HIGH. The PDATA pins
are turned off (High Impedance) whenever CSB or REB are HIGH or when WEB is LOW. The chip will only
drive these pins when both CSB and REB are LOW and WEB is HIGH. One can also ground the REB pin
and use the WEB pin as a read/write direction control and use the CSB pin as a control I/O strobe.
SDA
SCL
Figure 8 - I
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C Example of transferring 11001101 on SDA
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12-Mbit Frame Buffer / FIFO
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Preliminary Datasheet
Video Imaging Product
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August 8, 2006 LDS.3312 O
LF3312
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