lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 18

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Configuration Register Map
Instruction Register 8 (dflt = 10_00_0_111)
7:6 = WIDTH[1:0]
5:4 = Reserved
3
2:0 = OPMODE
Instruction Register 9 (dflt = 00_000_000)
7:6 = TRS_SYNC[1:0]
5
4
3
2:0 = FLAG_SET
Instruction Register A (dflt = 00000000)
7
6
5
4
3
2
1
0
Instruction Register B (dflt = 00_00_00_00)
7:4 = BFLAG_CTL
3:0 = AFLAG_CTL
Instruction Register C (dflt = 0000_0000)
7:4 = BASE_ADDR
3:0 = CASCADE
= MARK_ACTIVE_RESET
= B_FLD
= A_FLD
= MARK_SEL
= BSET_catch
= ASET_catch
= RSET_b_sel
= RCLR_b_sel
= BSET_b_sel
= BCLR_b_sel
= ASET_b_sel
= ACLR_b_sel
(00: ignore embedded TRS)
(0: frame sync - use falling F-bit from TRS)
(0: frame sync - use falling F-bit from TRS)
(0: use marked address - not user defined address)
(000: trigger empty, full on 1/80, 79/80)
(10: 10 bits)
(Make equal to 00)
(Make equal to 0)
(111: Two-Channel Asynchronous FIFO)
(0: setting B pointer does not MARK its new value)
(0: setting A pointer does not MARK its new value)
(0: RSET is falling edge triggered)
(0: RCLR is falling edge triggered)
(0: BSET is falling edge triggered)
(0: BCLR is falling edge triggered)
(0: ASET is falling edge triggered)
(0: ACLR is falling edge triggered)
18
(0000: lowest-address chip in cascade sequence)
(0000: single chip - no cascade of multiple chips)
(00: BPE, BPF are part-empty, -full)
(00: APE, APF are part-empty, -full)
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
August 8, 2006 LDS.3312 O
LF3312