lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 13

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
LOGIC Devices Incorporated
Input/Output
Controls
Detailed Signal Definition
PDATA7-0 - Parallel Microprocessor Interface Data Port
PDATA7-0 is the 8-bit data port for the parallel microprocessor interface. When inactive becomes high
impedance.
SDA - Serial Data I/O
SDA is the standard bidirectional data pin of a two-wire serial microprocessor interface.
External pullup is required on SDA.
BOUT11-0 - Data Output B
In two-channel modes(OPMODES 4-7), BOUT11-0 is the 12-bit registered data output port. BOUT[11]
is always the MSB. In 10-bit mode, bits 1 and 0 are tristated. In 8-bit mode, bits 3-0 are tristated.
All active bits are updated on each rising edge of RCLK when BREN is LOW. In OPMODE 0-3 ,
BOUT11-0 can act as the upper word of the 24bit external address ADDR if ROW_LENGTH is equal to
0, or Y-coordinate address if ROW_LENGTH is some value other than zero. BOUT11-0 represents a
portion of the read address port when executing an RSET, if and only if AREN=0, MARKSEL=1, BCLR=1.
BOUT11-0 represents a portion of the write address portwhen executing an ASET, if and only if AWEN=0,
ACLR=1, BSET=1. For more details on RSET and ASET, please refer to their signal definitions.
ACLR - Channel A Write Pointer Clear
When ACLR is brought LOW, the next rising edge of AWCLK will bring the current value on AIN[11:0] into
memory Channel A, address 0. Whenever ACLR is HIGH, the destination for AIN[11:0] will be controlled
by ASET. The user may program ACLR such that either its falling edge or its LOW state is active. If its
LOW state is active, holding this pin LOW will hold the write address in its zero position continuously. This
control takes effect only when AWEN is LOW.
BCLR - Channel B Write Pointer Clear / Channel A Write Random Select
In dual-channel modes (OPMODE = 4-7), this pin clears the Channel B Write Pointer, in the same manner
that ACLR clears the Channel A Write Pointer, and the user may program it to be falling edge or LOW state
active. In single-channel modes (OPMODE = 0-3), this pin and control MARKSEL govern the action of
RSET. In OPMODES 4-7, this control takes effect only when BWEN is LOW.
ASET - Channel A Write Pointer Set
This control is active only when ACLR is HIGH. Bringing ASET LOW will cause the next rising edge of
AWCLK to bring the current value on AIN[11:0] into memory A, at the address specified by ALAT, or
if OPMODE = 0-3 and BSET = 1, at the address whose Cartesian coordinates are present on BOUT
and BIN. Whenever ASET and ACLR are HIGH, the next rising edge of AWCLK will bring the current
AIN[11:0] data value into the next-higher address in sequence. ASET may be programmed to be either
edge-triggered, in which case it affects the write pointer for only one clock cycle following a falling edge,
after which incrementing resumes, or level-triggered, in which case it affects the write pointer until it is
brought HIGH. For continuous random access write operation, holding ASET LOW and programming it
to be level-triggered will provide the needed continuous write pointer override. This control takes effect
only when AWEN is LOW.
BSET - Channel B Write Pointer Set
In two-channel modes (OPMODE = 4-7), this pin’s impact on the B write pointer is analogous to that
of ASET on the A write pointer, and the user may program the pin’s action to be either edge- or level-
triggering. In one-channel modes, BSET determines whether ASET forces the write address pointer to
ALAT (BSET = 0) or to BOUT,BIN (BSET = 1). In OPMODES 4-7, this control takes effect only when
BWEN is LOW.
13
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
August 8, 2006 LDS.3312 O
LF3312