lf3312 LOGIC Devices Incorporated, lf3312 Datasheet - Page 12

• Manufacturer Part Number: lf3312
• Description: 12-mbit Frame Buffer / Fifo
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
Power
Clocks
Inputs
LOGIC Devices Incorporated
VCC
+1.8V power supply. All pins must be connected.
VCC
+3.3V power supply. All pins must be connected.
AWCLK - Write Clock A
Data present on AIN11-0 is written into the LF3312 on the rising edge of AWCLK when AWEN was LOW
for the previous rising edge of AWCLK.
BWCLK - Write Clock B
In two-channel modes(OPMODES 4-7), data present on BIN11-0 is written into the LF3312 on the rising
edge of BWCLK when BWEN is LOW. In one-channel modes(OPMODES 0-3), BWCLK must be tied
to AWCLK.
RCLK - Read Clock
In single channel modes, data is read from the LF3312 and presented on the output port (AOUT11-0)
after a rising edge of RCLK while AREN and AOE are LOW. In two-channel mode, data is also read
from the LF3312 and presented on the output port (BOUT11-0) after a rising edge of RCLK while BREN
and BOE are LOW.
AIN11-0 - Data Input A
AIN11-0 is the 12-bit registered data input port. Bit 11 is the MSB in all modes. AIN1-0 are ignored in
10-bit mode and AIN3-0 are ignored in 8-bit mode. Any such unused inputs should either be tied to
ground or driven to proper logic levels by external logic.
BIN11-0 - Data Input B
In dual-channel modes (OPMODES 4-7), BIN11-0 is the 12-bit registered data input port in all dual channel
FIFO modes. Bit 11 is the MSB in all modes. BIN1-0 are ignored in 10-bit mode and BIN3-0 are ignored
in 8-bit mode. Unused inputs should be tied off to ground or driven to proper logic levels by external logic.
In single-channel modes (OPMODE 0-3), BIN11-0 can act as a 24bit external address port (ADDR).
CHIP_ADDR6-0 - Chip Address (CA6-0)
CHIP_ADDR6-0 determines the LF3312’s address on the two-wire microprocessor bus. Each LF3312
chip’s 7-bit two-wire serial microprocessor interface address is equal to its CHIP_ADDR6-0.
SCL - Serial Clock Input
SCL is a standard two-wire serial microprocessor interface clock pin. With this chip, it functions as a
dedicated input, since this part cannot be the master on an two-wire serial microprocessor interface.
ADDR23-0 - External Random Access Read/Write Address Port
(OPMODE 0-3) ADDR23-0 is a virtual 24-bit memory address port, available in single channel modes.
ADDR23-0 is a concatenation of the BIN and BOUT data ports. BIN11-0 specifies ADDR11-0 (X/Column-
coordinate) and BOUT11-0 specifies ADDR23-12 (Y/Row-coordinate). The 24bit address is a purely linear
address when the instruction register ROW_LENGTH is equal to 0(default). When ROW_LENGTH is a
non-zero value, the memory is set to have a row (line) length of ROW_LENGTH.
PADDR5-0 - Parallel Microprocessor Interface Address Port
PADDR5-0 is the 6-bit address port for the parallel microprocessor interface. When inactive, it transitions
to a high impedance state.
Detailed Signal Definitions
INT
O
- Output Driver Power Supply
- Internal Core Power Supply
12
12-Mbit Frame Buffer / FIFO
Preliminary Datasheet
Video Imaging Product
August 8, 2006 LDS.3312 O
LF3312