xr16c2852ij Exar Corporation, xr16c2852ij Datasheet
xr16c2852ij
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xr16c2852ij Summary of contents
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FEBRUARY 2005 GENERAL DESCRIPTION 1 The XR16C2852 (2852 dual universal asynchronous receiver and transmitter (UART). The device operates at 2.97V to 5.5V and is pin-to-pin compatible to Exar’s ST16C2552 and XR16L2752. The 2852 register set is compatible ...
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... SSIGNMENT XTAL1 GND 12 XTAL2 CHSEL INTB 17 ORDERING INFORMATION ART UMBER ACKAGE XR16C2852CJ 44-PLCC XR16C2852IJ 44-PLCC 39 RXA 38 TXA 37 DTRA# 36 RTSA# 35 MFA# XR16C2852 34 INTA 44-pin PLCC 33 VCC 32 TXRDYB# 31 RIB# 30 CDB# 29 DSRB PERATING EMPERATURE ANGE 0° ...
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REV. 2.1.1 PIN DESCRIPTIONS Pin Description 44-PLCC N T AME YPE DATA BUS INTERFACE Address data lines [2:0]. These 3 address lines select one of the internal registers in UART channel A/B during ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS Pin Description 44-PLCC N T AME YPE RXA 39 I UART channel A Receive Data or infrared receive data. Normal receive data input must idleHIGH. The infrared receiver ...
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REV. 2.1.1 Pin Description 44-PLCC N T AME YPE RTSB UART channel B Request-to-Send (active low) or general purpose output. This port must be asserted prior to using auto RTS flow control, see EFR[6], ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 1.0 PRODUCT DESCRIPTION The XR16C2852 (2852) integrates the functions of 2 enhanced 16C550 Universal Asynchrounous Receiver and Transmitter (UART). Each UART is independently controlled having its own set of device configuration ...
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REV. 2.1.1 2.0 FUNCTIONAL DESCRIPTIONS 2.1 CPU Interface The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and write transactions. The 2852 data interface supports the Intel compatible ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS CS 2.5 Channel A and B Internal Registers Each UART channel in the 2852 has a set of enhanced registers for control, monitoring and data loading and unloading. ...
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REV. 2.1 TXRDY# ABLE FCR -0=0 BIT P INS (FIFO D ) ISABLED RXRDY# A/B LOW = 1 byte HIGH = no data TXRDY# A/B LOW = THR empty HIGH = byte in THR 2.8 INTA and ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS F IGURE The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant, fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100ppm frequency tolerance) ...
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REV. 2.1.1 16 divisor between 1 and (2 -1) to obtain a 16X sampling rate clock of the serial data rate. The sampling rate clock is used by the transmitter for data bit shifting and receiver for data sampling. ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.11.1 Transmit Holding Register (THR) - Write Only The transmit holding register is an 8-bit register providing a data interface to the host processor. The host writes transmit data byte to ...
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REV. 2.1 IGURE RANSMITTER PERATION IN Transmit Data Byte Auto CTS Flow Control (CTS# pin) Flow Control Characters (Xoff1/2 and Xon1/2 Reg. Auto Software Flow Control 16X Clock 2.12 Receiver The receiver section contains an ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS IGURE ECEIVER PERATION IN NON 16X Clock Receive Data Byte and Errors F 10 IGURE ECEIVER PERATION IN 16X Clock Receive Data Shift Register (RSR) ...
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REV. 2.1.1 2.13 Auto RTS (Hardware) Flow Control Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS# output is used to request remote unit to suspend/resume data transmission. The auto ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS F 11. A RTS CTS F IGURE UTO AND Local UART UARTA Receiver FIFO Trigger Reached Auto RTS Trigger Level Transmitter Auto CTS Monitor Assert RTS# to Begin Transmission 1 RTSA# ...
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REV. 2.1.1 2.16 Auto Xon/Xoff (Software) Flow Control When software flow control is enabled characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the programmed values, the 2852 will halt transmission (TX) as soon ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS host is ready to transmit next polling data packet again, it only has to load data bytes to the transmit FIFO. The transmitter automatically re-asserts RTS# output (LOW) prior sending the ...
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REV. 2.1.1 2.20 Sleep Mode with Auto Wake-Up The 2852 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. All of these conditions must be ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 2.21 Internal Loopback The 2852 UART provides an internal loopback capability for system diagnostic purposes. The internal loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular ...
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REV. 2.1.1 3.0 UART INTERNAL REGISTERS Each of the UART channel in the 2852 has its own set of configuration registers selected by address lines A0, A1 and A2 with CS# and CHSEL selecting the channel. The complete register ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS . T 8: INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE RHR RD Bit ...
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REV. 2.1 INTERNAL REGISTERS DESCRIPTION. ABLE DDRESS EG EAD A2- AME RITE DLL RD/WR Bit DLM RD/WR Bit AFR ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 4.3.1 IER versus Receive FIFO Interrupt Mode Operation When the receive FIFO (FCR BIT and receive interrupts (IER BIT are enabled, the RHR interrupts (see ISR bits ...
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REV. 2.1.1 IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1) • Logic 0 = Disable the software flow control, receive Xoff interrupt (default). • Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS ] T ABLE P ISR R RIORITY EGISTER EVEL ...
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REV. 2.1.1 FCR[3]: DMA Mode Select Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details. • Logic 0 = Normal Operation (default). • Logic 1 = DMA Mode. FCR[5:4]: Transmit FIFO Trigger Select ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS 4.6 Line Control Register (LCR) - Read/Write The Line Control Register is used to specify the asynchronous data communication format. The word or character length, the number of stop bits, and ...
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REV. 2.1.1 LCR[5]: TX and RX Parity Select If the parity bit is enabled, LCR BIT-5 selects the forced parity format. • LCR BIT-5 = logic 0, parity is not forced (default). • LCR BIT-5 = logic 1 and ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS AFR[2:1]: MF# Output Select These bits select a signal function for output on the MF# A/B pins. These signal function are described as: OP2#, BAUDOUT#, or RXRDY#. Only one signal function ...
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REV. 2.1.1 MCR[6]: Infrared Encoder/Decoder Enable • Logic 0 = Enable the standard modem receive and transmit input/output interface (default). • Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the infrared ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS LSR[7]: Receive FIFO Data Error Flag • Logic FIFO error (default). • Logic global indicator for the sum of all error bits in the RX ...
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REV. 2.1.1 MSR[7]: CD Input Status Normally this bit is the complement of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the MCR register. The CD# input may be used as a general ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS EMSR[5:4]: Extended RTS Hysteresis EMSR EMSR[7:6]: Reserved 4.13 FIFO Level Register (FLVL) ...
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REV. 2.1.1 4.15 Device Identification Register (DVID) - Read Only This register contains the device ID (0x12 for XR16C2852). Prior to reading this register, DLL and DLM should be set to 0x00. 4.16 Device Revision Register (DREV) - Read ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS FCTR[6]: Scratchpad Swap • Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode. • Logic 1 = FIFO Count register (Read-Only), Enhanced Mode ...
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REV. 2.1.1 EFR[4]: Enhanced Function Bits Enable Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5 modified. After modifying any enhanced bits, EFR bit-4 can be ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS T 16: UART RESET CONDITIONS FOR CHANNEL A AND B ABLE REGISTERS DLL DLM AFR RHR THR IER FCR ISR LCR MCR LSR MSR SPR EMSR FLVL EFR XON1 XON2 XOFF1 ...
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REV. 2.1.1 ABSOLUTE MAXIMUM RATINGS Power Supply Range Voltage at Any Pin Operating Temperature Storage Temperature Package Dissipation TYPICAL PACKAGE THERMAL RESISTANCE DATA Thermal Resistance (44-PLCC) ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TA=0 NLESS OTHERWISE NOTED 5.0V ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS .. F 14. XR16C2852 VOL S IGURE INK 0.00 0.10 0.20 F 15. XR16C2852 VOH S IGURE OURCE 12 ...
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REV. 2.1.1 AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S P YMBOL ARAMETER CLK Clock Pulse Duration OSC Oscillator Frequency OSC External Clock Frequency T Address Setup Time AS ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS AC ELECTRICAL CHARACTERISTICS TA (-40 + WHERE APPLICABLE S P YMBOL ARAMETER T Delay From Center of Start To Reset TXRDY# SRT ...
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REV. 2.1 IGURE ATA US EAD IMING A0 CS# IOR# T RDV D0- IGURE ATA US RITE IMING A0 CS# IOW# ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS F 20 & I IGURE ECEIVE EADY NTERRUPT RX Start D0:D7 Bit INT RXRDY# IOR# (Reading data out of RHR & I IGURE RANSMIT EADY ...
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REV. 2.1 & I IGURE ECEIVE EADY NTERRUPT Start Bit RX D0:D7 D0: Stop Bit INT T SSR RXRDY# First Byte is Received in RX FIFO IOR# (Reading data out of RX FIFO) ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS F 24 & I IGURE RANSMIT EADY NTERRUPT Start TX FIFO Bit Empty TX S D0:D7 (Unloading) IER[1] ISR is read enabled INT* TX FIFO fills up Data in ...
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REV. 2.1.1 PACKAGE DIMENSIONS (44 PIN PLCC Note: The control dimension is the millimeter column SYMBOL ...
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XR16C2852 2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS Revision History Date Revision July 1999 Rev 1.0.0 Initial datasheet. April 2002 Rev 2.0.0 Changed to standard style format. Internal Registers are described in the order they are listed in the ...
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... REV. 2.1.1 EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user’ ...
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XR16C2852 REV. 2.1.1 GENERAL DESCRIPTION .................................................................................................1 A ................................................................................................................................................1 PPLICATIONS F .....................................................................................................................................................1 EATURES F 1. XR16C2852 B D IGURE LOCK IAGRAM ..................................................................................................................................................... 2 IGURE IN UT SSIGNMENT .................................................................................................................................2 ORDERING INFORMATION PIN DESCRIPTIONS .........................................................................................................3 1.0 PRODUCT DESCRIPTION ...
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TO 5.5V DUAL UART WITH 128-BYTE FIFOS 4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 24 4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 25 4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 25 4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... ...