xr16c2852ij Exar Corporation, xr16c2852ij Datasheet - Page 12

• Manufacturer Part Number: xr16c2852ij
• Description: 2.97v To 5.5v Dual Uart With 128-byte Fifos
• Manufacturer: Exar Corporation

XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input
register to the transmit FIFO of 128 bytes when FIFO operation is enabled by FCR bit-0. Every time a write
operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data
location.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
amount of data in the FIFO falls below its programmed trigger level. The transmit empty interrupt is enabled by
IER bit-1. The TSR flag (LSR bit-6) is set when TSR/FIFO becomes empty.
F
2.11.1
2.11.2
2.11.3
IGURE
7. T
Transmit Holding Register (THR) - Write Only
Transmitter Operation in non-FIFO Mode
Transmitter Operation in FIFO Mode
RANSMITTER
Clock
16X
Data
Byte
O
PERATION IN NON
Transmit Shift Register (TSR)
Transmit
Register
Holding
-FIFO M
(THR)
ODE
12
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
M
S
B
TXNOFIFO1
L
S
B
xr
REV. 2.1.1