xr16c2852ij Exar Corporation, xr16c2852ij Datasheet - Page 48

• Manufacturer Part Number: xr16c2852ij
• Description: 2.97v To 5.5v Dual Uart With 128-byte Fifos
• Manufacturer: Exar Corporation

XR16C2852
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
Revision History
July 1999
April 2002
May 2004
February 2005
Date
Rev 1.0.0
Rev 2.0.0
Rev 2.1.0
Rev 2.1.1
Revision
Initial datasheet.
Changed to standard style format. Internal Registers are described in the order they
are listed in the Internal Register Table. Clarified timing diagrams. Corrected Auto
RTS Hysteresis table. Renamed Rclk (Receive Clock) to Bclk (Baud Clock) and tim-
ing symbols. Added T
Changed to single column format. Added device status to ordering information.
Clarified sleep mode conditions. Clarified pin descriptions- changed from using logic
1 and logic 0 to HIGH (VCC) and LOW (GND) for input and output pin descriptions.
Added VOL sink current and VOH source current charts
Devices with top mark date code of "F2 YYWW" and newer have 5V tolerant inputs
(except for XTAL1) and have 0 ns address hold time (T
updated to 0x06.
Corrected datasheet to show that all inputs are 5V tolerant (including XTAL1) in
devices with top mark date code of "F2 YYWW" and newer.
AH
48
, T
CS
and OSC.
Description
AH
(Figure 14
). DREV register was
xr
and
Figure
REV. 2.1.1
15).