xr16c2852ij Exar Corporation, xr16c2852ij Datasheet - Page 35

• Manufacturer Part Number: xr16c2852ij
• Description: 2.97v To 5.5v Dual Uart With 128-byte Fifos
• Manufacturer: Exar Corporation

xr
REV. 2.1.1
This register contains the device ID (0x12 for XR16C2852). Prior to reading this register, DLL and DLM should
be set to 0x00.
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Register
which is located in the general register set when FCTR bit-6 = 1.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7] =
0) can be read via this register.
This register controls the XR16C2852 new functions.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See
FCTR[2]: IrDa RX Inversion
•
•
FCTR[3]: Auto RS-485 Direction Control
•
•
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
4.15
4.16
4.17
4.18
4.19
Logic 0 = Select RX input as encoded IrDa data.
Logic 1 = Select RX input as active high encoded IrDa data.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from low to high one bit time after the last stop bit of the last character is shifted out. Also,
the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The RTS#
output pin will automatically return to a logic low when a data byte is loaded into the TX FIFO.
Table 10 on page
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
Trigger Level / FIFO Data Count Register (TRG) - Write-Only
FIFO Data Count Register (FC) - Read-Only
Feature Control Register (FCTR) - Read/Write
27.
FCTR B
0
0
1
1
IT
-5
T
ABLE
FCTR B
14: T
0
1
0
1
IT
RIGGER
-4
35
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
T
ABLE
Table 13 on page 34
S
ELECT
T
ABLE
for more details.
XR16C2852