xr20v2172 Exar Corporation, xr20v2172 Datasheet - Page 30

• Manufacturer Part Number: xr20v2172
• Description: Two Channel I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
• Manufacturer: Exar Corporation

XR20V2172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
MCR[2]: OP1# / TCR and TLR Enable
OP1# is not available as an output pin on the V2172. But it is available for use during Internal Loopback Mode
(MCR[4] = 1). In the Internal Loopback Mode, this bit is used to write the state of the modem RI# interface
signal.
This bit is also used to select between the MSR and TCR registers at address offset 0x6 and the SPR and TLR
registers at address offset 0x7.
MCR[3]: OP2# Output
OP2# is not available as an output on the V2172 but can be controlled in internal loopback mode.
•
•
MCR[4]: Internal Loopback Enable
•
•
MCR[5]: Xon-Any Enable (requires EFR bit-4=1 to write to this bit)
•
•
MCR[6]: Infrared Encoder/Decoder Enable
•
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the
infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface requirement.
While in this mode, the infrared TX output will be idling LOW.
ONLY)” ON PAGE 19.
Logic 0 = OP2# output set HIGH(default).
Logic 1 = OP2# output set LOW.
Logic 0 = Disable loopback mode (default).
Logic 1 = Enable local loopback mode, see loopback section and
Logic 0 = Disable Xon-Any function (default).
Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.
The RX character will be loaded into the RX FIFO, unless the RX character is an Xon or Xoff character and
the V2172 is programmed to use the Xon/Xoff flow control.
Logic 0 = Enable the standard modem receive and transmit input/output interface (default).
EFR[4]
EFR[4] MCR[2] Register at Address Offset 0x6
0
1
1
0
1
1
Table 12
T
T
ABLE
ABLE
MCR[2] Register at Address Offset 0x7
X
0
1
X
0
1
12: R
13: R
and
Modem Status Register (MSR)
Modem Status Register (MSR)
Trigger Control Register (TCR)
Scratchpad Register (SPR)
Scratchpad Register (SPR)
Trigger Level Register (TLR)
EGISTER AT
EGISTER AT
Table 13
30
below shows how these registers are accessed.
A
A
DDRESS
DDRESS
SEE”INFRARED MODE (UART CHANNEL B
O
O
FFSET
FFSET
Figure
0
0
14.
X
X
6
7
REV. 1.0.0