xr20v2172 Exar Corporation, xr20v2172 Datasheet - Page 33

• Manufacturer Part Number: xr20v2172
• Description: Two Channel I2c/spi Uart With 64-byte Fifo And Rs232 Transceiver
• Manufacturer: Exar Corporation

REV. 1.0.0
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a power off-on cycle. There are also two other
registers (TLR and FIFO Rdy) that share the same address location as the Scratch Pad Register. See
Table
This register replaces MSR and is accessible only when MCR[2] = 1. This 8-bit register is used to store the RX
FIFO threshold levels to halt/resume transmission during hardware or software flow control.
TCR[3:0]: RX FIFO Halt Level
A value of 0-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the Halt Level. When the RX
FIFO is greater than or equal to this value, the RTS# output will be de-asserted if Auto RTS flow control is used
or the XOFF character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that
this value is greater than the RX Trigger Level.
TCR[7:4]: RX FIFO Resume Level
A value of 0-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the Resume Level. When the
RX FIFO is less than or equal to this value, the RTS# output will be re-asserted if Auto RTS flow control is used
or the XON character(s) will be transmitted if Auto XON/XOFF flow control is used. It is recommended that this
value is less than the RX Trigger Level.
This register replaces SPR and is accessible under the conditions listed in
to store the RX and TX FIFO trigger levels used for interrupts.
TLR[3:0]: TX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[3:0] multiplied by 4) can be selected as the TX FIFO Trigger Level.
When the number of available spaces in the TX FIFO is greater than or equal to this value, a Transmit Ready
interrupt is generated. For any non-zero value, TCR[3:0] will be used as the TX FIFO Trigger Level. If
TCR[3:0] = 0x0, then the TX FIFO Trigger Level is the value selected by FCR[5:4]. See
TLR[7:4]: RX FIFO Trigger Level
A value of 4-60 (decimal value of TCR[7:4] multiplied by 4) can be selected as the RX FIFO Trigger Level.
When the number of characters received in the RX FIFO is greater than or equal to this value, a Receive Data
Ready interrupt is generated (a Receive Data Timeout interrupt is independent of the RX FIFO Trigger Level
and can be generated any time there is at least 1 byte in the RX FIFO and the RX input has been idle for the
timeout period described in
used as the RX FIFO Trigger Level. If TCR[7:4] = 0x0, then the RX FIFO Trigger Level is the value selected by
FCR[7:6]. See
This register reports the number of spaces available in the TX FIFO. If the TX FIFO is empty, the TXLVL
register will report that there are 64 spaces available. If the TX FIFO is full, the TXLVL register will report that
there are 0 spaces available.
This register reports the number of characters available in the RX FIFO. If the RX FIFO is empty, the RXLVL
register will report that there are 0 characters available. If the RX FIFO is full, the RXLVL register will report
that there are 64 characcters available.
This register is used to program the direction of the GPIO pins. Bit-7 to bit-0 controls GPIO7 to GPIO0.
•
•
4.11
4.12
4.13
4.14
4.15
Logic 0 = set GPIO pin as input
Logic 1 = set GPIO pin as output
13.
Transmission Control Register (TCR) - Read/Write (requires EFR bit-4 = 1)
Trigger Level Register (TLR) - Read/Write (requires EFR bit-4 = 1)
Transmit FIFO Level Register (TXLVL) - Read-only
Receive FIFO Level Register (RXLVL) - Read-only
GPIO Direction Register (IODir) - Read/Write
Table
10.
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO AND RS232 TRANSCEIVER
“Section 2.9, Receiver” on page
33
14). For any non-zero value, TCR[7:4] will be
Table
13. This 8-bit register is used
Table
XR20V2172
10.