wm8961 Wolfson Microelectronics plc, wm8961 Datasheet - Page 67
![no-image](/images/no-image-200.jpg)
wm8961
Manufacturer Part Number
wm8961
Description
Ultra-low Power Stereo Codec With 1w Stereo Class D Speaker Drivers And Ground Referenced Headphone Drivers
Manufacturer
Wolfson Microelectronics plc
Datasheet
1.WM8961.pdf
(116 pages)
- Current page: 67 of 116
- Download datasheet (2Mb)
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WM8961
_LOCATION
WSEQ
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0
1
2
3
4
5
6
7
8
9
WM8961
8’h08
8’hFE
8’h1C
8’h19
8’h48
8’h1A
8’h45
8’h45
8’h02
8’h03
8’h03
8’h3D
8’hFE
8’h07
8’h45
8’h45
8’hFE
8’h5
8’h20
8’h21
8’h19
8’h3C
8’hFE
8’h19
8’h20
8’h21
8’hFE
8’h5
8’h00
8’h01
_INDEX
REG
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b1
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b0
1’b1
1’b0
1’b0
1’b0
EOS
The default values of the write control sequencer are given in Table 50
3’h0
3’h0
3’h1
3’h2
3’h0
3’h3
3’h4
3’h4
3’h6
3’h6
3’h0
3’h5
3’h0
3’h1
3’h4
3’h4
3’h0
3’h0
3’h1
3’h1
3’h4
3’h5
3’h0
3’h1
3’h1
3’h1
3’h0
3’h0
3’h0
3’h1
WIDTH
START
4’h4
4’h0
4’h3
4’h6
4’h0
4’h5
4’h0
4’h1
4’h0
4’h0
4’h8
4’h2
4’h0
4’h2
4’h2
4’h3
4’h0
4’h3
4’h4
4’h4
4’h1
4’h2
4’h0
4’h2
4’h4
4’h4
4’h0
4’h3
4’h7
4’h7
8’h1
8’h0
8’h3
8’h3
8’h01
8’hF
8’h11
8’h19
8’h65
8’h65
8’h01
8’h33
8’h0
8’h0
8’h1D
8’h1F
8’h0
8’h0
8’h03
8’h03
8’h19
8’h33
8’h00
8’h3
8’h0
8’h0
8’h00
8’h1
8’h01
8’h03
DATA
DELAY
4’h0
4’h0
4’h0
4’h0
4’h6
4’h0
4’h0
4’h0
4’h0
4’h0
4’h0
4’hC
4’h0
4’h0
4’h0
4’h0
4’h0
4’h8
4’h0
4’h0
4’h0
4’hC
4’h0
4’h0
4’h0
4’h0
4’h0
4’h8
4’h0
4’h0
CLK_DSP_ENA = 1
Dummy Write for
expansion
BUFDCOPEN = 1,
BUFIOEN = 1 ; Enable
current bias circuits
VMIDSEL = 01, VREF
= 1 ; VMID can be
brought up fast,
master bias enable
Enable Charge pump,
wait 4.5ms
LOUT1_PGA = 1,
ROUT1_PGA = 1,
DACL = 1, DACR = 1
Set HPL_ENA,
HPR_ENA
Set HPL_EN_DLY,
HPR_EN_DLY
LOUT1VOL to -20dB
(7’b1100101)
ROUT1VOL to -20dB
(7’b1100101)
OUT1VU
Enable Servo on
outputs, trigger
startup, wait 256ms
Dummy Write for
expansion
AIF WL = 16 bit
Set HPL_ENA_OUTP
& HPR_ENA_OUTP
Set HPL_RMV_SHRT
& HPR_RMV_SHRT
Dummy Write for
expansion
DAC Soft unmute, wait
16.5ms
LMICBOOST = 11
RMICBOOST = 11
AINL = 1, AINR = 1,
MICB = 1
Enable Servo on
inputs, trigger startup,
wait 256ms
Dummy Write for
expansion
ADCL = 1, ADCR = 1
LMICBOOST = 00
RMICBOOST = 00
Dummy Write for
expansion
DAC Soft mute, wait
16.5ms
LINMUTE = 1
RINMUTE = 1, IPVU
COMMENT
CUMULATIVE
PP, August 2009, Rev 3.1
DELAY
0.0005
0.0005
0.0005
0.0005
0.0045
0.0005
0.0005
0.0005
0.0005
0.0005
0.0005
0.2560
0.0005
0.0005
0.0005
0.0005
0.0005
0.0165
0.0005
0.0005
0.0005
0.2560
0.0005
0.0005
0.0005
0.0005
0.0005
0.0165
0.0005
0.0005
Pre-Production
STARTUP
0.0005
0.0010
0.0015
0.0020
0.0065
0.0070
0.0075
0.0080
0.0085
0.0090
0.0095
0.2655
0.2660
0.2665
0.2670
0.2675
0.2680
0.2845
0.0005
0.0010
0.0015
0.2575
0.2580
0.2585
0.2590
0.2595
0.2600
0.0165
0.0170
0.0175
TIME
67
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