wm8961 Wolfson Microelectronics plc, wm8961 Datasheet - Page 82

• Manufacturer Part Number: wm8961
• Description: Ultra-low Power Stereo Codec With 1w Stereo Class D Speaker Drivers And Ground Referenced Headphone Drivers
• Manufacturer: Wolfson Microelectronics plc

R252 (FCh General test 1
w
R60 (3Ch)DC Servo 0
R61 (3Dh)DC Servo 1
R92 (5Ch) Write Sequencer
R93 (5Dh) Write Sequencer
R40 (28h) LOUT2 volume
R41 (29h) ROUT2 volume
R47 (2Fh) Pwr Mgmt (3)
R48 (30h) Additional
R49 (31h) Class D Control
R51 (33h) Class D Control
R56 (38h) Clocking 4
R57 (39h) DSP Sidetone 0
R58 (3Ah) DSP Sidetone 1
R63 (3Fh) DC Servo 3
R65 (41h) DC Servo 5
R68 (44h) Analogue PGA
R69 (45h) Analogue HP 0
R71 (47h) Analogue HP 2
R72 (48h) Charge Pump 1
R82 (52h) Charge Pump B
R87 (57h) Write Sequencer
R88 (58h) Write Sequencer
R89 (59h) Write Sequencer
R90 (5Ah) Write Sequencer
R91 (5Bh) Write Sequencer
WM8961
REG
path
Control (4)
1
2
Bias
1
2
3
4
5
6
7
NAME
15
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
13
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
11
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
10
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0 WSEQ_EO
0
0
0
0
0
0
9
WSEQ_AB
SPKVU SPKLZC
SPKVU SPKRZC
ORT
S
0
0
0 SPKR_ENA SPKL_ENA 0
0
0
0
0 DCS_ENA_
0 DCS_ENA_
0
0
0
0 HPL_RMV_
0
0
0
0
0
0
0
0
8
HPL_VOL[2:0]
WSEQ_STA
CHAN_HPL
CHAN_INL
CLK_DCS_DIV[3:0]
SHORT
RT
0
0
0
0
0
0
0
0
0
0
0
0
0
7
ADCR_DAC_SVOL[3:0]
ADCL_DAC_SVOL[3:0]
_STARTUP
_STARTUP
DCS_TRIG
DCS_TRIG
HPL_ENA_
WSEQ_DATA_WIDTH[2:0]
OUTP
_HPL
_INL
0
0
0
0 DCS_FILT_BW_SER
0
0
0
0
0
0
0
0
6
HPL_ENA_
WSEQ_EN
DLY
0
0
0
0 DCS_TRIG
0 DCS_TRIG
0
0
0
A
0
0
0
5
IES[1:0]
HPR_VOL[2:0]
_SERIES_H
_SERIES_I
HPL_ENA HPR_RMV_
WSEQ_ADDR[7:0]
DCS_SERIES_NO_HP[6:0]
WSEQ_DATA[7:0]
NL (K)
PL
0
0
0
0
0
0
0
0
0
0
WSEQ_START_INDEX[5:0]
4
SPKRVOL[6:0]
SPKLVOL[6:0]
CLK_SYS_RATE[3:0]
CHAN_HPR
ADC_TO_DACR[1:0
DCS_ENA_
DCS_ENA_
ADC_TO_DACL[1:0] 0
CHAN_INR
WSEQ_WRITE_INDEX[4:0]
SHORT
0
0
0
0
0
0
0
0
0
0
3
WSEQ_DATA_START[3:0]
_STARTUP
_STARTUP
HPR_ENA_
DCS_TRIG
DCS_TRIG
WSEQ_DELAY[3:0]
OUTP
_HPR
CLASSD_ACGAIN[2:0]
_INR
HP_BIAS_BOOST[2:0]
PP, August 2009, Rev 3.1
HP_PGAS_BIAS[2:0]
0 TEMP_SHU
0
0
0
0
0
0
0
2
HPR_ENA_
TSENSENMBSEL 0023h
CP_DYN_PWR[1:0] 0000h
ARA_ENA A UTO_INC 0001h
DLY
T
0
0
0
0
0
0
0
1
_SERIES_H
TEMP_WA
DCS_TRIG
_SERIES_I
DCS_TRIG
WSEQ_BU
Pre-Production
HPR_ENA 0000h
CP_ENA 0000h
NR (K)
RN
PR
SY
0
0
0
0
0
0
DEFAULT
015Eh
01FBh
0000h
0000h
0000h
0000h
0003h
0106h
0000h
0000h
0000h
0000h
0010h
0003h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
82