a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 111

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

Figure 2-33 • Input DDR Timing Diagram
Table 2-164 • Input DDR Propagation Delays
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD1
DDRISUD2
DDRIHD1
DDRIHD2
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage supply levels, refer to
Military-Case Conditions: T
Timing Characteristics
t
t
1
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (fall)
Data Setup for Input DDR (rise)
Data Hold for Input DDR (fall)
Data Hold for Input DDR (rise)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal Time for Input DDR
Asynchronous Clear Recovery Time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width HIGH for Input DDR
Clock Minimum Pulse Width LOW for Input DDR
Maximum Frequency for Input DDR
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
J
t
DDRICLKQ1
= 125°C, Worst-Case VCC = 1.14 V for A3PE600L and A3PE3000L
Description
4
2
R e v i s i o n 0
3
5
t
DDRICLKQ2
t
DDRISUD
Table 2-5 on page 2-8
Military ProASIC3/EL Low Power Flash FPGAs
6
4
5
7
t
DDRIHD
0.38
0.54
0.39
0.34
0.00
0.00
0.64
0.79
0.00
0.31
0.19
0.31
0.28
TBD
–1
t
for derating values.
8
DDRIRECCLR
6
7
0.45
0.63
0.46
0.40
0.00
0.00
0.75
0.93
0.00
0.36
0.22
0.36
0.32
TBD
Std.
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 97