a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 115

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

Table 2-169 • Output DDR Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDROCLKQ
DDRISUD1
DDROSUD2
DDROHD1
DDROHD2
DDROCLR2Q
DDROREMCLR
DDRORECCLR
DDROWCLR1
DDROCKMPWH
DDROCKMPWL
DDOMAX
For specific junction temperature and voltage supply levels, refer to
Military-Case Conditions: T
Clock-to-Out of DDR for Output DDR
Data_F Data Setup for Output DDR
Data_R Data Setup for Output DDR
Data_F Data Hold for Output DDR
Data_R Data Hold for Output DDR
Asynchronous Clear-to-Out for Output DDR
Asynchronous Clear Removal Time for Output DDR
Asynchronous Clear Recovery Time for Output DDR
Asynchronous Clear Minimum Pulse Width for Output DDR
Clock Minimum Pulse Width HIGH for the Output DDR
Clock Minimum Pulse Width LOW for the Output DDR
Maximum Frequency for the Output DDR
J
= 125°C, VCC = 1.425 V for A3PE600L/A3PE3000L
Description
R e v i s i o n 0
Table 2-5 on page 2-8
Military ProASIC3/EL Low Power Flash FPGAs
0.74
0.40
0.40
0.00
0.00
0.85
0.00
0.24
0.19
0.31
0.28
TBD
for derating values.
–1
0.87
0.47
0.47
0.00
0.00
1.00
0.00
0.28
0.22
0.36
0.32
TBD
Std.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 101