a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 149

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a3p1000-1pqg208m

Manufacturer Part Number
a3p1000-1pqg208m
Description
Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
Manufacturer
Actel Corporation
Datasheet
Table 2-192 • FIFO
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
F
Note:
ENS
ENH
BKS
BKH
DS
DH
CKQ1
CKQ2
RCKEF
WCKFF
CKAF
RSTFG
RSTAF
RSTBQ
REMRSTB
RECRSTB
MPWRSTB
CYC
MAX
For specific junction temperature and voltage supply levels, refer to
derating values.
Worst Military-Case Conditions: T
REN_B, WEN_B Setup Time
REN_B, WEN_B Hold Time
BLK_B Setup Time
BLK_B Hold Time
Input Data (DI) Setup Time
Input Data (DI) Hold Time
Clock HIGH to New Data Valid on DO (flow-through)
Clock HIGH to New Data Valid on DO (pipelined)
RCLK HIGH to Empty Flag Valid
WCLK HIGH to Full Flag Valid
Clock HIGH to Almost Empty/Full Flag Valid
RESET_B LOW to Empty/Full Flag Valid
RESET_B LOW to Almost Empty/Full Flag Valid
RESET_B LOW to Data Out LOW on DO (flow-through)
RESET_B LOW to Data Out LOW on DO (pipelined)
RESET_B Removal
RESET_B Recovery
RESET_B Minimum Pulse Width
Clock Cycle Time
Maximum Frequency for FIFO
Description
R e v i s i o n 0
J
= 125°C, V
Military ProASIC3/EL Low Power Flash FPGAs
CC
= 1.425 V for A3P1000
Table 2-6 on page 2-8
1.66
0.02
0.40
0.00
0.22
0.00
2.84
1.08
2.07
1.96
7.45
2.04
7.38
0.34
1.81
0.26
3.89
1.11
1.11
257
–1
0.03
Std.
1.95
0.47
0.00
0.26
0.00
3.33
1.27
2.43
2.31
8.76
2.40
8.67
1.31
1.31
0.40
2.12
0.30
4.57
219
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2- 135
for

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