a3p1000-1pqg208m Actel Corporation, a3p1000-1pqg208m Datasheet - Page 13

• Manufacturer Part Number: a3p1000-1pqg208m
• Description: Fpga Proasic 3 Family 1m Gates 130nm Cmos Technology 1.5v 208-pin Pqfp
• Manufacturer: Actel Corporation

The CCC block has these key features:
Additional CCC specifications:
Global Clocking
Military ProASIC3/EL devices have extensive support for multiple clocking domains. In addition to the
CCC and PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
I/Os with Advanced I/O Standards
The military ProASIC3/EL family of FPGAs features a flexible I/O structure, supporting a range of
voltages (1.5 V, 1.8 V, 2.5 V, and 3.3 V). In addition, 1.2 V I/O operation is supported for military
ProASIC3EL devices. Military ProASIC3/EL FPGAs support different I/O standards, including single-
ended, differential, and voltage-referenced (military ProASIC3EL). The I/Os are organized into banks,
with two, four, or eight (military ProASIC3EL only) banks per device. The configuration of these banks
determines the I/O standards supported. For military ProASIC3EL, each I/O bank is subdivided into V
minibanks, which are used by voltage-referenced I/Os. V
in a given minibank share a common V
configured as a V
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
Military ProASIC3EL banks support LVPECL, LVDS, B-LVDS, and M-LVDS. B-LVDS and M-LVDS can
support up to 20 loads.
•
•
•
•
•
•
•
•
•
•
•
•
Wide input frequency range (f
Output frequency range (f
2 programmable delay types for clock skew minimization
Clock frequency synthesis
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration.
Output duty cycle = 50% ± 1.5% or better
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used
Maximum acquisition time is 300 µs
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns
Four precise phases; maximum misalignment between adjacent phases of 40 ps × 250 MHz /
f
Single-data-rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)
Double-data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II).
OUT_CCC
REF
pin, the remaining I/Os in that minibank will be able to use that reference voltage.
OUT_CCC
IN_CCC
) = 0.75 MHz up to 250 MHz
REF
) = 1.5 MHz up to 250 MHz
R e v i s i o n 0
line. Therefore, if any I/O in a given V
REF
Military ProASIC3/EL Low Power Flash FPGAs
minibanks contain 8 to 18 I/Os. All the I/Os
REF
minibank is
REF
1 -7