s71pl512nd0 Meet Spansion Inc., s71pl512nd0 Datasheet - Page 50
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s71pl512nd0
Manufacturer Part Number
s71pl512nd0
Description
Two S29pl256n Devices 32 M X 16-bit Cmos 3.0-volt Only Simultaneous Read/write, Page-mode Flash Memory
Manufacturer
Meet Spansion Inc.
Datasheet
1.S71PL512ND0.pdf
(90 pages)
- Current page: 50 of 90
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48
Device returns to reading array.
PASS. Write Lock Register
Address XXXh, Data 90h
Address XXXh, Data 00h
Exit Command:
Yes
Enter Lock Register Command:
Program Lock Register Data
Address XXXh, Data A0h
Perform Polling Algorithm
Address 555h, Data 40h
Address 555h, Data AAh
Address 2AAh, Data 55h
Address 77h*, Data PD
(see Write Operation Status
Write Unlock Cycles:
Figure 10.2 Lock Register Program Algorithm
S29PL-N MirrorBit™ Flash Family
flowchart)
DQ5 = 1?
Wait 4 µs
Write
Done?
No
Yes
to return to reading array.
FAIL. Write rest command
P r e l i m i n a r y
No
Unlock Cycle 1
Unlock Cycle 2
XXXh = Address don’t care
* Not on future devices
Program Data (PD): See text for Lock Register
definitions
Caution:
Error condition (Exceeded Timing Limits)
Lock data may only be progammed once.
S29PL-N_M0_A4 November 23, 2005
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