s71pl512nd0 Meet Spansion Inc., s71pl512nd0 Datasheet - Page 85
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s71pl512nd0
Manufacturer Part Number
s71pl512nd0
Description
Two S29pl256n Devices 32 M X 16-bit Cmos 3.0-volt Only Simultaneous Read/write, Page-mode Flash Memory
Manufacturer
Meet Spansion Inc.
Datasheet
1.S71PL512ND0.pdf
(90 pages)
- Current page: 85 of 90
- Download datasheet (2Mb)
26 AC Characteristics
27 Timing Diagrams
27.1
February 3, 2005 pSRAM_15_A2
(Ta = -40°C to 85°C, V
Read Timings
Note: t
Note: Address Controlled, CS1#=OE#=V
Address
Data Out
Symbol
WP
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
(min)=70ns for continuous write operation over 50 times.
t
t
t
t
t
t
t
t
WHZ
t
OLZ
BHZ
OHZ
BLZ
WC
CW
AW
BW
WR
DW
OW
RC
CO
OE
HZ
OH
WP
DH
AA
BA
LZ
PC
PA
AS
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
UB#, LB# Access Time
Chip Select to Low-Z Output
UB#, LB# Enable to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
UB#, LB# Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
Page Cycle Time
Page Access Time
Write Cycle Time
Chip Select to End of Write
Address Set-up Time
Address Valid to End of Write
UB#, LB# Valid to End of Write
Write Pulse Width
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
Previous Data Valid
P r e l i m i n a r y
CC
Figure 27.1 Timing Waveform of Read Cycle(1)
= 2.7 to 3.1 V)
Paramet er
IL
pSRAM Type 2
, CS2= WE# = V
t
OH
IH
t
AA
, UB# and/or LB#=V
t
RC
(3 for 64Mb)
55 (Note 1)
IL
.
Min
70
10
10
25
70
60
60
60
30
—
—
—
—
—
5
0
0
5
0
0
0
5
0
0
Speed Bins
70ns
Data Valid
Max
70
70
35
70
25
25
25
20
25
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
83
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