am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 10

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

PIN DESCRIPTION
A19–A0
A21–A20
DQ15–DQ0
CE#f
CE1#s
CE2s
OE#
WE#
UB#s
LB#s
RESET#
V
V
V
V
NC
RDY
CLK
AVD#
November 1, 2002
CC
IO
CC
SS
f
f
s
= 20 Address Inputs (Common)
= 2 Address Inputs (Flash)
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
= Chip Enable 1 (SRAM)
= Chip Enable 2 (SRAM)
= Output Enable (Common)
= Write Enable (Common)
= Upper Byte Control (SRAM)
= Lower Byte Control (SRAM)
= Hardware Reset Pin, Active Low
= Flash 1.8 volt-only single power
= Input & Output Buffer Power Supply
= SRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
= Ready output; indicates the status of
= CLK is not required in asynchronous
= Address Valid input. Indicates to de-
supply (see Product Selector Guide
for speed options and voltage sup-
ply tolerances)
must be tied to V
the Burst read. Low = data not valid
at expected time. High = data valid.
mode. In burst mode, after the initial
word is output, subsequent active
edges of CLK increment the internal
address counter.
vice that the valid address is present
on the address inputs (A21–A0).
Low = for asynchronous mode, indi-
cates valid address; for burst mode,
causes starting address to be
latched.
CC
f.
P R E L I M I N A R Y
Am42BDS640AG
WP#
ACC
LOGIC SYMBOL
20
A21–A20
CE#f
CE1#s
CE2s
OE#
WE#
WP#
RESET#
UB#s
LB#s
ACC
AVD#
A19–A0
CLK
= Hardware write protect input. At V
= At V
High = device ignores address in-
puts
disables program and erase func-
tions in the two outermost sectors.
Should be at V
tions.
automatically places device in un-
lock bypass mode. At V
sectors. Should be at V
conditions.
ID
DQ15–DQ0
, accelerates programming;
RDY
IH
for all other condi-
16
IH
IL
for all other
, locks all
IL
9
,