am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 66

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

SRAM AC CHARACTERISTICS
Write Cycle
Notes:
1. WE# controlled.
2. t
3. t
4. t
5. A write occurs during the overlap (t
November 1, 2002
asserting UB#s or LB#s for a single byte operation or simultaneously asserting UB#s and LB#s for a double byte operation. A
write ends at the earliest transition when CE1#s goes high and WE# goes high. The t
to the end of write.
CW
WR
AS
Parameter
Symbol
is measured from the address valid to the beginning of write.
is measured from CE1#s going low to the end of write.
is measured from the end of write to the address change. t
t
t
t
t
t
t
t
t
t
WHZ
t
t
Address
CS1#s
CS2s
UB#s, LB#s
WE#
Data In
Data Out
WC
AW
BW
WP
WR
DW
OW
Cw
AS
DH
Description
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
UB#s, LB#s to End of Write
Write Pulse Time
Write Recovery Time
Write to Output High-Z
Data to Write Time Overlap
Data Hold from Write Time
End Write to Output Low-Z
(See Note 6)
(See Note 9)
Figure 36. SRAM Write Cycle—WE# Control
WP
) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when
High-Z
(See Note 4)
P R E L I M I N A R Y
t
AS
Am42BDS640AG
t
WR
WHZ
(See Note 2)
(See Note 2)
applied in case a write ends as CE1#s or WE# going high.
t
AW
t
(See Note 5)
WC
t
t
t
CW
BW
CW
t
WP
t
DW
Data Valid
Max
Min
Min
Min
Min
Min
Min
Min
Min
Min
Min
min
WP
is measured from the beginning of write
t
WR
t
(54 MHz)
DH
t
D8, D9
(See Note 3)
OW
70
60
60
60
50
20
30
0
0
0
0
5
High-Z
(See Note 9)
(See Note 7)
(40 MHz)
C8, C9
85
70
70
70
60
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
65