am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 2

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

Am42BDS640AG
Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
Am29BDS640G 64 Megabit (4 M x 16-Bit) CMOS 1.8 Volt-only, Simultaneous Operation,
Burst Mode Flash Memory and 16 Mbit (1 M x 16-Bit) Static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Flash Memory Features
ARCHITECTURAL ADVANTAGES
PERFORMANCE CHARCTERISTICS
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Power supply voltage of 1.65 to 1.95 volt
High performance
— Access time as fast as 70 ns
Package
— 93-Ball FBGA
Operating Temperature
— –40°C to +85°C
Single 1.8 volt read, program and erase (1.65 to 1.95 volt)
Manufactured on 0.17 µm process technology
Simultaneous Read/Write operation
— Data can be continuously read from one bank while
— Zero latency between read and write operations
— Four bank architecture: 16Mb/16Mb/16Mb/16Mb
Programmable Burst Interface
— 2 Modes of Burst Read Operation
— Linear Burst: 8, 16, and 32 words with wrap-around
— Continuous Sequential Burst
Sector Architecture
— Eight 8 Kword sectors and one hundred twenty-six 32
— Banks A and D each contain four 8 Kword sectors and
— Eight 8 Kword boot sectors, four at the top of the address
Minimum 1 million erase cycle guarantee per sector
20-year data retention at 125°C
Read access times at 54/40 MHz
— Burst access times of 13.5/20 ns @ 30 pF at industrial
— Asynchronous random access times of 70 ns (at 30 pF)
— Synchronous latency of 87.5/95 ns
executing erase/program functions in other bank
Kword sectors
thirty-one 32 Kword sectors; Banks B and C each contain
thirty-two 32 Kword sectors
range, and four at the bottom of the address range
temperature range
PRELIMINARY
Refer to AMD’s Website (www.amd.com) for the latest information.
HARDWARE FEATURES
SOFTWARE FEATURES
SRAM Features
Power dissipation (typical values, C
— Burst Mode Read: 10 mA
— Simultaneous Operation: 25 mA
— Program/Erase: 15 mA
— Standby mode: 0.2 µA
Software command sector locking
Handshaking: host monitors operations via RDY output
Hardware reset input (RESET#)
WP# input
— Write protect (WP#) function protects sectors 0, 1 (bottom
ACC input: Acceleration function reduces programming
time; all sectors locked when ACC = V
CMOS compatible inputs, CMOS compatible outputs
Low V
Supports Common Flash Memory Interface (CFI)
Software command set compatible with JEDEC 42.4
standards
Data# Polling and toggle bits
Erase Suspend/Resume
— Suspends or resumes an erase operation in one sector to
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
Power dissipation
— Operating: 3 mA maximum
— Standby: 15 µA maximum
CE1s# and CE2s Chip Select
Power down features using CE1s# and CE2s
Data retention supply voltage: 1.0 to 2.2 volt
Byte data control: LB#s (DQ7–DQ0), UB#s (DQ15–DQ8)
boot) or sectors 132 and 133 (top boot), regardless of sector
protect status
read data from, or program data to, other sectors
program command sequences
CC
write inhibit
Publication# 26445
Issue Date: November 1, 2002
Rev: B Amendment/0
L
IL
= 30 pF)