am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 44

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

AC CHARACTERISTICS
Notes:
1. Figure shows total number of wait states set to seven cycles. The total number of wait states can be programmed from two
2. If any burst address occurs at a 64-word boundary, one additional clock cycle is inserted, and is indicated by RDY.
3. The device is in synchronous mode.
4. A17 = 1.
Note: Figure assumes 7 wait states for initial access, 54 MHz clock, and automatic detect synchronous read. D0–D7 in data
waveform indicate the order of data within a given 8-word address range, from lowest to highest. Data will wrap around within
the 8 words non-stop unless the RESET# is asserted low, or AVD# latches in another address. Starting address in figure is the
7th address in range (A6). See “Requirements for Synchronous (Burst) Read Operation”. The Set Configuration Register
command sequence has been written with A18=1; device will output RDY with valid data.
November 1, 2002
DQ15-DQ0
DQ15-DQ0
A21-A0
cycles to seven cycles. Clock is set for active rising edge.
A21-A0
AVD#
CE#f
RDY
AVD#
CLK
OE#
RDY
CE#
CLK
OE#
Hi-Z
t
t
f
AVDS
ACS
Hi-Z
t
t
ACH
AAS
Aa
Aa
1
t
AVC
t
t
CES
CAS
t
AVD
t
AVD
t
AAH
2
Figure 14. 8-word Linear Burst with Wrap Around
1
t
OE
Figure 13. Synchronous Burst Mode Read
t
OE
3
7 cycles for initial access shown.
2
t
7 cycles for initial access shown.
t
IACC
ACC
t
IACC
P R E L I M I N A R Y
4
18.5 ns typ. (54 MHz)
3
Am42BDS640AG
t
ACC
5
4
6
5
t
RACC
7
t
RDYS
6
D6
t
t
RACC
BDH
D7
7
t
RDYS
t
BACC
Da
D0
t
BDH
Da + 1
t
D1
BACC
D5
t
Da + n
t
CEZ
OEZ
D6
Hi-Z
Hi-Z
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