am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 5

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 63
4
Read Cycle ............................................................................. 63
Figure 24. Alternate Synchronous Program Operation Timings ..... 54
Figure 25. Chip/Sector Erase Command Sequence ....................... 55
Figure 26. Accelerated Unlock Bypass Programming Timing......... 56
Figure 27. Data# Polling Timings (During Embedded Algorithm) ... 57
Figure 28. Toggle Bit Timings (During Embedded Algorithm)......... 57
Figure 29. Synchronous Data Polling Timings/Toggle Bit Timings . 58
Figure 30. Latency with Boundary Crossing ................................... 59
Figure 31. Latency with Boundary Crossing
into Program/Erase Bank ................................................................ 60
Figure 32. Example of Wait States Insertion (Standard
Handshaking Device) ...................................................................... 61
Figure 33. Back-to-Back Read/Write Cycle Timings ....................... 62
Figure 34. SRAM Read Cycle—Address Controlled....................... 63
Figure 35. SRAM Read Cycle ......................................................... 64
P R E L I M I N A R Y
Am42BDS640AG
Flash Erase And Programming Performance
Flash Latchup Characteristics. . . . . . . . . . . . . . . 68
Package Pin Capacitance . . . . . . . . . . . . . . . . . . 68
Flash Data Retention . . . . . . . . . . . . . . . . . . . . . . 68
SRAM Data Retention . . . . . . . . . . . . . . . . . . . . . 69
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 70
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 71
Write Cycle ............................................................................. 65
FSC093—93-Ball Fine-Pitch Grid Array 8 x 11.6 mm ............ 70
Revision A (May 20, 2002) ..................................................... 71
Figure 36. SRAM Write Cycle—WE# Control ................................ 65
Figure 37. SRAM Write Cycle—CE1#s Control ............................. 66
Figure 38. SRAM Write Cycle—UB#s and LB#s Control ............... 67
Figure 39. CE1#s Controlled Data Retention Mode....................... 69
Figure 40. CE2s Controlled Data Retention Mode......................... 69
November 1, 2002
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