am42bds640ag Meet Spansion Inc., am42bds640ag Datasheet - Page 35

• Manufacturer Part Number: am42bds640ag
• Description: 64 Megabit 4 M ? 16-bit Cmos 1.8 Volt-only, Simultaneous Operation, Burst Mode Flash Memory And 16 Mbit 1 M ? 16-bit Static Ram Preliminary
• Manufacturer: Meet Spansion Inc.

DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional sectors
are selected for erasure, the entire time-out also
applies after each additional sector erase command.
When the time-out period is complete, DQ3 switches
from a “0” to a “1.” If the time between additional sector
erase commands from the system can be assumed to
be less than 50 µs, the system need not monitor DQ3.
See also the Sector Erase Command Sequence sec-
tion.
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
4. The system may read either asynchronously or synchronously (burst) while in erase suspend. RDY will function exactly as in
34
Standard
Suspend
Refer to the section on DQ5 for more information.
is in progress. The device outputs array data if the system addresses a non-busy bank.
non-erase-suspended mode.
Erase
Mode
Mode
Embedded Program Algorithm
Embedded Erase Algorithm
Erase-Suspend-Program
Erase-Suspend-
Read (Note 4)
Status
Erase
Suspended Sector
Non-Erase
Suspended Sector
Table 16. Write Operation Status
P R E L I M I N A R Y
Am42BDS640AG
(Note 2)
DQ7#
DQ7#
DQ7
Data
0
1
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all
further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the
system software should check the status of DQ3 prior
to and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 16
status bits.
No toggle
Toggle
Toggle
Toggle
shows the status of DQ3 relative to the other
DQ6
Data
(Note 1)
Data
DQ5
0
0
0
0
Data
DQ3
N/A
N/A
N/A
November 1, 2002
1
No toggle
(Note 2)
Toggle
Toggle
DQ2
Data
N/A