th50vsf3583aasb TOSHIBA Semiconductor CORPORATION, th50vsf3583aasb Datasheet

th50vsf3583aasb

Manufacturer Part Number

th50vsf3583aasb

Description

Sram And Flash Memory Mixed Multi-chip Package

Manufacturer

TOSHIBA Semiconductor CORPORATION

Datasheet

1.TH50VSF3583AASB.pdf (50 pages)

Current page: 1 of 50
Download datasheet (637Kb)

TENTATIVE

SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

DESCRIPTION

33,554,432-bit flash memory. The CIOS and CIOF inputs can be used to select the optimal memory configuration.

The power supply. FLASH MEMORY a Simultaneous Read/Write operation so that data can be read during a Write

or Erase operation. The TH50VSF3582/3583AASB can range from 2.67 V to 3.3 V. The TH50VSF3582/3583AASB is

available in a 69-pin BGA package, making it suitable for a variety of design applications.

FEATURES

•

PIN ASSIGNMENT

•

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal

The TH50VSF3582/3583AASB is a mixed multi-chip package containing a 8,388,608-bit Full CMOS SRAM and a

can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the

buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and

to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or

damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the

most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling

Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..

equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are

neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or

failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy

control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document

shall be made at the customer’s own risk.

Power supply voltage

Data retention supply voltage

Current consumption

Block erase architecture for flash memory

Organization

Case: CIOF = V

CIOF

Operating: 45 mA maximum (CMOS level)

Standby:

8 × 8 Kbytes

63 × 64 Kbytes

CCs

CCf

CCs

CIOS

= 2.67 V~3.3 V

= 1.5 V~3.3 V

CEF

2,097,152 words of 16 bits

4,194,304 words of 8 bits

10 µA maximum (SRAM CMOS level)

10 µA maximum (FLASH)

TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS

DQ0

DQ8

, CIOS = V

Flash Memory

DQ10

DQ1

DQ9

DQ2

A18

A17

(TOP VIEW)

RESET

DQ11

DQ3

(×16, ×16)

CCf

/ACC

CE2S

CIOS

DQ4

A20

524,288 words of 16 bits

1,048,576 words of 8 bits

CCs

DQ13 DQ15 CIOF

DQ12

DQ6

DQ5

A19

A10

SRAM

DQ14

DQ7

A11

A12

A13

A14

A15

A16

•

Function mode control for flash memory

Flash memory functions

Erase and Program cycle for flash memory

Boot block architecture for flash memory

Package

PIN NAMES

Compatible with JEDEC-standard commands

Simultaneous Read/Write operations

Auto-Program

Auto Chip Erase, Auto Block Erase

Auto Multiple-Block Erase

Program Suspend/Resume

Block-Erase Suspend/Resume

Data Polling/Toggle Bit function

Block Protection/Boot Block Protection

Automatic Sleep, Hidden ROM Area Supports

Common Flash Memory Interface (CFI)

Byte/Word Mode

TH50VSF3582AASB: Top boot block

TH50VSF3583AASB: Bottom boot block

P-FBGA69-1209-0.80A3: 0.31 g (typ.)

DQ0~DQ15

LB , UB

A0~A21

RESET

cycles (typical)

A12S

A12F

CIOS

CIOF

CEF

CCs

CCf

/ACC

, CE2S Chip Enable Inputs for SRAM

TH50VSF3582/3583AASB

Address Inputs

A12 Input for SRAM

A12 Input for Flash Memory

A18 Input for SRAM

Data Inputs/Outputs

Chip Enable Input for Flash Memory

Output Enable Input

Write Enable Input

Data Byte Control Input

Ready/Busy Output

Hardware Reset Input

Write Protect/Program Acceleration Input

Word Enable Input for SRAM

Word Enable Input for Flash Memory

Power Supply for SRAM

Power Supply for Flash Memory

Ground

Not Connected

Don’t Use

2001-06-08 1/50

000707EBA2

Related parts for th50vsf3583aasb

th50vsf3583aasb Summary of contents

Page 1

... SRAM 10 cycles (typical) Boot block architecture for flash memory • 524,288 words of 16 bits TH50VSF3582AASB: Top boot block 1,048,576 words of 8 bits TH50VSF3583AASB: Bottom boot block 1,048,576 words of 8 bits Package • P-FBGA69-1209-0.80A3: 0.31 g (typ.) PIN NAMES A0~A21 A12S ...

Page 2

PIN ASSIGNMENT (TOP VIEW) • Case: CIOF = V , CIOS = V (×16, × /ACC RESET ...

Page 3

BLOCK DIAGRAM A0~A21 WP /ACC RESET CEF CIOF CE2S UB LB CIOS MODE SELECTION OPERATION MODE CEF Flash Read SRAM Read H ...

Page 4

... ID CODE TABLE TYPE Manufacturer Code TH50VSF3582AASB Device Code TH50VSF3583AASB Verify Block Protect Note (1) DQ8~DQ15 are Hi-Z in Byte mode (2) BA: Block address (3) 0001H: Protected block 0000H: Unprotected block TH50VSF3582/3583AASB A20~A12 ( (1) A0 ...

Page 5

... Bank Address and ID Read Address (A6, A1, A0) Bank Address = A20~A15 Manufacturer Code = ( Device Code = ( (5) ID: ID Data 0098H - Manufacturer Code 009AH - Device Code (TH50VSF3582AASB) 009CH - Device Code (TH50VSF3583AASB) 0001H - Protected Block SECOND BUS THIRD BUS FOURTH BUS WRITE CYCLE WRITE CYCLE ...

Page 6

BLOCK ERASE ADDRESS TABLES TH50VSF3582AASB (top boot block) BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 L L BA1 L L BA2 L L BA3 L L BK0 BA4 L L BA5 ...

Page 7

BLOCK ADDRESS BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA32 BA33 BA34 BA35 BK4 BA36 BA37 H ...

Page 8

BLOCK ADDRESS BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 BA64 BA65 BA66 BK8 BA67 BA68 H ...

Page 9

... TH50VSF3583AASB (bottom boot block) BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA0 BA1 BA2 BA3 BK0 BA4 BA5 BA6 BA7 BA8 BA9 BA10 BK1 ...

Page 10

BLOCK ADDRESS BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA31 BA32 BA33 BA34 BK4 BA35 BA36 L ...

Page 11

BLOCK ADDRESS BANK BLOCK BANK ADDRESS # # A20 A19 A18 A17 A16 A15 A14 A13 A12 BA63 BA64 BA65 BA66 BK8 BA67 BA68 H ...

Page 12

... Kwords BA24~BA31 64 Kbytes 32 Kwords BA32~BA39 64 Kbytes 32 Kwords BA40~BA47 64 Kbytes 32 Kwords BA48~BA55 64 Kbytes 32 Kwords BA56~BA62 64 Kbytes 32 Kwords BA63~BA70 8 Kbytes TH50VSF3583AASB (bottom boot block) BLOCK SIZE BLOCK # BYTE MODE WORD MODE BA0~BA7 8 Kbytes BA8~BA14 64 Kbytes 32 Kwords BA15~BA22 64 Kbytes 32 Kwords BA23~BA30 64 Kbytes 32 Kwords BA31~BA38 ...

Page 13

ABSOLUTE MAXIMUM RATINGS SYMBOL PARAMETER Supply Voltage CC CCs CCf (1) V Input Voltage IN V Input/Output Voltage DQ T Operating Temperature opr P Power Dissipation D T Soldering Temperature (10 s) solder I Output Short Circuit ...

Page 14

RECOMMENDED DC OPERATING CONDITIONS SYMBOL PARAMETER V /V Power Supply Voltage CCs CCf V Input High-Level Voltage IH V Input Low-Level Voltage IL V Data Retention Voltage for SRAM DH V Flash Low-Lock Voltage LKO V High Voltage for WP ...

Page 15

DC CHARACTERISTICS ( -30°~85°C, V SYMBOL PARAMETER I Input Leakage Current IL Input Leakage Current I ILW ( WP /ACC pin) I SRAM Output High Current SOH I SRAM Output Low Current SOL I Flash Output ...

Page 16

AC CHARACTERISTICS (SRAM) ( -40°~85°C, V Read cycle SYMBOL t Read Cycle Time RC t Address Access Time ACC t Chip Enable ( Access Time CO1 t Chip Enable (CE2S) Access Time ...

Page 17

AC CHARACTERISTICS (FLASH MEMORY) READ CYCLE SYMBOL PARAMETER t Read Cycle Time RC t Address Access Time ACC t CEF Access Time Access Time OE t CEF to Output Low-Z CEE Output Low-Z OEE ...

Page 18

COMMAND WRITE/PROGRAM/ERASE CYCLE SYMBOL PARAMETER t Command Write Cycle Time CMD t Address Set-up Time / BYTE Set-up Time AS t Address Hold Time / BYTE Hold Time AH t Address Hold Time from WE High level AHW t Data ...

Page 19

SIMULTANEOUS READ/WRITE OPERATION The TH50VSF3582/3583AASB features a Simultaneous Read/Write operation. The Simultaneous Read/Write operation enables the device to simultaneously write data to or erase data from a bank while the device reads data from another bank. The TH50VSF3582/3583AASB has a ...

Page 20

ID Read Mode ID Read mode is used to read the device maker code and device code. The mode is useful for EPROM programmers to automatically identify the device type. In this method, simultaneous operation can be performed. Inputting an ...

Page 21

Command Write The TH50VSF3582/3583AASB utilizes the JEDEC command control standard for a single power supply 2 E PROM. A Command is executed by inputting an address and data into the Command register. The Command is written by inputting a pulse ...

Page 22

Auto-Program Mode The TH50VSF3582/3583AASB can be programmed in either byte or word units. The Auto Program mode is set using the Program command. The program address is latched on the falling edge of the WE signal and data is latched ...

Page 23

Program Suspend / Resume Mode Program Suspend is used to enable Data Read by suspending Write operation. The device receives a Program Suspend command in Write mode (including Write performed during Erase Suspend) but ignores the command in other modes. ...

Page 24

Auto Block / Multiple Block Erase Mode The Auto Block and Multiple Block Erase modes are set using the Block Erase command. The block address is latched on the falling edge of the WE signal in the sixth bus cycle. ...

Page 25

Block Protect Block Protection is a function to disable write and erase in block units. Applying V to RESET and inputting the Block Protect command performs block protection. The first cycle of ID the command sequence is the Setup command. ...

Page 26

... To exit Hidden ROM mode, use the Hidden ROM Mode Exit command. The device returns to Read mode. Hidden Rom Area Address Table BOOT BLOCK TYPE ARCHITECTURE TH50VSF3582AASB TOP BOOT BLOCK TH50VSF3583AASB BOTTOM BOOT BLOCK TH50VSF3582/3583AASB rather than V is input to RESET . Once the block is protected ...

Page 27

Common Flash Memory Interface (CFI) The TH50VSF3582/3583AASB conforms to the CFI. Information on device specifications and characteristics can be obtained via CFI. To read information from the device, input the Query command followed by the address. In Word mode, DQ8 ...

Page 28

... Block Protect/Unprotect scheme Simultaneous Operation 0: Not Supported 1: Supported Burst Mode 0: Not Supported Page Mode 0: Not Supported V Min voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV V Max voltage ACC DQ7~DQ4 DQ3~DQ0: 100 mV Top/Bottom Boot Block Flag 2: TH50VSF3582AASB 3: TH50VSF3583AASB Program Suspend 0: Not Supported 1: Supported 2001-06-08 28/50 ...

Page 29

HARDWARE SEQUENCE FLAGS FOR FLASH MEMORY The TH50VSF3582/3583AASB has a Hardware Sequence flag which allows the device status to be determined during an auto mode operation. The output data is read out using the same timing as that used when ...

Page 30

DQ3 (Block Erase timer) The Block Erase operation starts 50 µs (Erase Hold Time) after the rising edge the last command cycle. DQ3 outputs a 0 during the Block Erase Hold Time and a 1 when the ...

Page 31

DATA PROTECTION The TH50VSF3582/3583AASB features a function which makes malfunction or data damage difficult. Protection Against Program/Erase Caused by Low Supply Voltage To prevent malfunction at power on or power down, the device does not receive commands when V V ...

Page 32

TIMING DIAGRAMS FLASH READ/ID READ OPERATION Address CEF OEH D OUT SRAM READ CYCLE (see Note 1) Address CE2S Hi-Z OUT Data Invalid t ...

Page 33

SRAM WRITE CYCLE 1 ( -CONTROLLED) (see Note 4) WE Address CE2S See Note 2 OUT D See Note SRAM WRITE CYCLE 2 ( -CONTROLLED) ...

Page 34

SRAM WRITE CYCLE 3 (CE2S-CONTROLLED) (see Note 4) Address CE2S Hi-Z OUT D See Note SRAM WRITE CYCLE and Address ...

Page 35

FLASH COMMAND WRITE OPERATION This is the timing of the Command Write Operation. The timing which described follow pages is typically same as this page’s. WE Control • Address t AS CEF CEF Control • Address t ...

Page 36

FLASH ID READ OPERATION (Input command sequence) Address 555H t CMD CEF OE t OES WE D AAH IN D OUT Read Mode (Input ID Read Command Sequence) (Continued) Address 555H t CMD CEF AAH IN D ...

Page 37

FLASH AUTO-PROGRAM OPERATION ( Address 555H t CMD CEF OE t OES WE D AAH IN D OUT t VCS V CCf Note: Word Mode address shown. PA: Program address PD: Program data FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE OPERATION ...

Page 38

FLASH AUTO-PROGRAM OPERATION ( Address 555H 2AAH t CMD CEF OE t OES AAH D OUT t VCS V CCf Notes: Word mode address shown PA: Program address PD: Program data FLASH AUTO CHIP ERASE/AUTO BLOCK ERASE ...

Page 39

FLASH PROGRAM/ERASE SUSPEND OPERATION Address BK CEF B0H IN Hi-Z D OUT t SUSP Program/Erase Mode RA: Read address BK: Bank address FLASH PROGRAM/ERASE RESUME OPERATION Address RA CEF OE t OES WE t ...

Page 40

FLASH DURING AUTO-PROGRAM/ERASE OPERATION CEF FLASH HARDWARE RESET OPERATION WE RESET RESET FLASH READ AFTER Address RESET D Hi-Z OUT TH50VSF3582/3583AASB Command input sequence During operation t BUSY t RB ...

Page 41

FLASH HARDWARE SEQUENCE FLAG ( Last Address Command Address t CMD OEHP WE Last D Command IN Data DQ7 DQ0~DQ6 t BUSY PA: Program address BA: Block address FLASH HARDWARE SEQUENCE FLAG (Toggle Bit) ...

Page 42

FLASH BLOCK PROTECT OPERATION Address t CMD CEF VPS RESET D 60h IN D OUT Notes Block address Next Block address * : 01h ...

Page 43

TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES CEF CE2S Notes: (1) WE remains High during a Read cycle. ( goes Low (or CE2S goes High) at the same time as or after ...

Page 44

SRAM DATA RETENTION CHARACTERISTICS SYMBOL PARAMETER V Data Retention Supply Voltage for SRAM DH I SRAM Standby Current CCS4 t Chip-Deselect-to-Data-Retention-Mode Time CDR t Recovery Time r (1) Read cycle time -CONTROLLED DATA RETENTION MODE (see Note ...

Page 45

FLOWCHARTS OF FLASH MEMORY OPERATIONS Auto-Program Address = Address + 1 Note: Word mode command sequence is shown. TH50VSF3582/3583AASB Start Auto-Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes Auto-Program Completed Auto-Program command sequence (address/data) ...

Page 46

Fast Program Address = Address + 1 Fast Program Set command sequence (address/data) 555H/AAH 2AAH/55H 555H/20H TH50VSF3582/3583AASB Start Fast Program Set Command Sequence (see below) Fast Program Command Sequence (see below) DATA Polling or Toggle Bit No Last Address? Yes ...

Page 47

Auto-Erase Auto-Erase Command Sequence Auto Chip Erase command sequence (address/data) 555H/AAH 2AAH/55H 555H/80H 555H/AAH 2AAH/55H 555H/10H Note: Word mode command sequence is shown. TH50VSF3582/3583AASB Start (see below) DATA Polling or Toggle Bit Auto-Erase Completed Auto Block Erase / Multiple-Block Erase ...

Related keywords

th50vsf3583aasb datasheet
th50vsf3583aasb data sheet
th50vsf3583aasb pdf datasheet
th50vsf3583aasb component
th50vsf3583aasb part
th50vsf3583aasb distributor
th50vsf3583aasb RoHS
th50vsf3583aasb datasheet download