th50vsf3583aasb TOSHIBA Semiconductor CORPORATION, th50vsf3583aasb Datasheet - Page 44

• Manufacturer Part Number: th50vsf3583aasb
• Description: Sram And Flash Memory Mixed Multi-chip Package
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SRAM DATA RETENTION CHARACTERISTICS
Notes:
V
I
t
t
(1) Read cycle time
CE2S-CONTROLLED DATA RETENTION MODE (see Note 3)
CE
CCS4
CDR
r
(1)
(2)
(3)
DH
SYMBOL
1
S
-CONTROLLED DATA RETENTION MODE (see Note 1)
In
CE2S ≤ 0.2 V or CE2S ≥ V
When
transition of V
In CE2S-Controlled Data Retention Mode, Minimum Standby Current Mode is entered when
CE2S ≤ 0.2 V.
V
2.7 V
V
2.7 V
GND
GND
CE
CCs
CCs
V
V
V
IH
IH
IL
1
Data Retention Supply Voltage for SRAM
SRAM Standby Current
Chip-Deselect-to-Data-Retention-Mode Time
Recovery Time
CE
S
CE
V
V
CE2S
-Controlled Data Retention Mode, Minimum Standby Current Mode is entered when
1
CCs
CCs
S
1
S
is operating at the V
CCs
from 2.67 V to 2.3 V.
PARAMETER
CCs
(See Note 2)
V
V
t
CDR
DH
DH
t
− 0.2 V.
CDR
= 3.3 V
= 3.0 V
IH
level, the SRAM standby current is the same as I
Ta = −30°~85°C
Ta = −30°~40°C
Ta = −30°~85°C
Data Retention Mode
Data Retention Mode
V
CCs
(Ta = = = = -30°~85°C)
0.2 V
− 0.2 V
t
RC
MIN
1.5



0
(1)
TH50VSF3582/3583AASB
TYP.






(See Note 2)
t
r
t
2001-06-08 44/50
r
MAX
3.3
10


1
5
CCS3
during the
UNIT
µA
ns
ns
V