th50vsf3583aasb TOSHIBA Semiconductor CORPORATION, th50vsf3583aasb Datasheet - Page 18

• Manufacturer Part Number: th50vsf3583aasb
• Description: Sram And Flash Memory Mixed Multi-chip Package
• Manufacturer: TOSHIBA Semiconductor CORPORATION

COMMAND WRITE/PROGRAM/ERASE CYCLE
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SYMBOL
WELH
WEHH
WES
WEH
CMD
AS
AH
AHW
DS
DH
CES
CEH
CELH
CEHH
OES
OEHP
OEHT
BEH
VCS
BUSY
RP
READY
RB
RH
CEBTS
SUSP
RESP
SUSE
RESE
Command Write Cycle Time
Address Set-up Time / BYTE Set-up Time
Address Hold Time / BYTE Hold Time
Address Hold Time from WE High level
Data Set-up Time
Data Hold Time
Erase Hold Time
V
Program/Erase Valid to
Program Suspend Command to Suspend Mode
Program Resume Command to Program Mode
Erase Suspend Command to Suspend Mode
Erase Resume Command to Erase Mode
CEF Set-up Time to WE Active
CEF Hold Time from WE High Level ( WE Control)
CEF Low-Level Hold Time
CEF High-Level Hold Time
OE Set-up Time
OE Hold Time (Toggle, Data Polling)
OE High-Level Hold Time (Toggle)
RESET Low-Level Hold Time
RESET Low-Level to Read Mode
RY
RESET Recovery Time
CEF Set-up time BYTE Transition
WE Low-Level Hold Time
WE High-Level Hold Time
WE Set-up time to CEF Active
WE Hold Time from CEF High Level ( CEF Control)
CCf
/
BY
Set-up Time
Recovery Time
PARAMETER
RY
/
BY
Delay
( WE Control)
( WE Control)
( WE Control)
( CEF Control)
( CEF Control)
( CEF Control)
MIN
500
500
70
40
20
40
40
20
40
20
90
20
50
50






0
0
0
0
0
0
0
0
5
30pF
TH50VSF3582/3583AASB
LOAD CAPACITANCE
MAX
1.5



















90

20



15
1
1
MIN
500
500
80
40
20
40
40
20
40
20
90
20
50


50




2001-06-08 18/50
0
0
0
0
0
0
0
0
5
100pF
MAX
1.5
90
20
15























1
1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs