th50vsf3583aasb TOSHIBA Semiconductor CORPORATION, th50vsf3583aasb Datasheet - Page 21

• Manufacturer Part Number: th50vsf3583aasb
• Description: Sram And Flash Memory Mixed Multi-chip Package
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Release ID Read or CFI mode
Clear the Command resister
Release the lock state when automatic operation ends abnormally
Stop automatic operation in progress
All stops of operation other than the above, and return to Read mode
BYTE
Command Write
E
is written by inputting a pulse to WE with CEF = V
be written by inputting a pulse to CEF with WE = V
edge of either WE or CEF . The data is latched on the rising edge of either WE or CEF . DQ0 to DQ7 are
valid for data input and DQ8 to DQ15 are ignored.
register and enters Read mode. When an undefined command is input, the Command register is reset and the
device enters Read mode.
Software Reset
or CFI mode to Read mode, releases the lock state when automatic operation ends abnormally, or clears the
Command register.
Hardware Reset
the device ends the operation in progress and enters Read mode after t
applied during data overwrite such as a Write or Erase operation, data at that address or block become
undefined.
= V
command are allowed after the device enters Read mode.
Comparison with Software Reset and Hardware Reset
input to CIOF, the device operates in Word mode. Read data or write commands using DQ0 to DQ15. When V
is input to CIOF, read data or write commands using DQ0 to DQ7. A12F is used as the lowest address. DQ8 to
DQ14 become high-impedance.
2
The TH50VSF3582/3583AASB utilizes the JEDEC command control standard for a single power supply
To cancel input of the command sequence mid-way, use the Reset command. The device resets the Command
Apply a software reset by inputting a Read/Reset command. Software reset returns the device from ID Read
A hardware reset initializes the device and sets it to Read mode. When a pulse is input to RESET for t
After a hardware reset the device enters Read mode when RESET = V
CIOF is used select Word mode (16 bits) or Byte mode (8 bits) for the TH50VSF3582/3583AASB. When V
PROM. A Command is executed by inputting an address and data into the Command register. The Command
IL
. The DQ pins are High-Impedance when RESET = V
/WORD Mode
ACTION
IL
IL
and OE = V
( CEF control). The address is latched on the falling
IL
SOFTWARE RESET
. The Read operation sequence and input of any
Invalid
Invalid
Valid
Valid
Valid
IH
READY
TH50VSF3582/3583AASB
( WE control). The command can also
IH
and Standby mode when RESET
. Note that if a hardware reset is
2001-06-08 21/50
HARDWARE RESET
Valid
Valid
Valid
Valid
Valid
IH
RP
IL
is
,