am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet
am49pdl129bh85it
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am49pdl129bh85it Summary of contents
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Am49PDL129BH Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, ...
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ADVANCE INFORMATION Am49PDL127BH/Am49PDL129BH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit ( 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 32 Mbit ( 16-Bit) CMOS Pseudo Static RAM with Page Mode DISTINCTIVE CHARACTERISTICS ...
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HARDWARE FEATURES Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data WP#/ACC ...
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GENERAL DESCRIPTION The Am29PDL127H/Am29PDL129H are 128 Mbit, 3.0 volt-only Page Mode and Simultaneous Read/Write Flash memory devices organized as 8 Mwords. The word-wide data (x16) appears on DQ15-DQ0. The devices can be pro- ...
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TABLE OF CONTENTS PDL127 Configuration ........................................................... 3 PDL129H Configuration ......................................................... 3 Product Selector Guide . . . . . . . . . . . . . . . . . . . ...
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Figure 13. Timing Diagram for Alternating Between Pseudo SRAM and Flash................................................. 62 Flash AC Characteristics . . . . . . . . . . . . . . . . . . ...
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PRODUCT SELECTOR GUIDE Part Number Standard Voltage Range: Speed Option V = 2.7–3 Max Access Time, ns Page Access Time, ns CE#f1 Access, ns OE# Access, ns MCP BLOCK DIAGRAM (A22) ...
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CONNECTION DIAGRAM–PDL129 LB UB A18 A17 G1 ...
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CONNECTION DIAGRAM–PDL127 LB UB A18 A17 G1 ...
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PIN DESCRIPTION A20– Address Inputs (Common) A21 = Address Inputs (Flash) A22 = Address Input (PDL127 only) (Flash) DQ15–DQ0 = 16 Data Inputs/Outputs (Common) CE#f1 = Chip Enable 1 (Flash) CE#f2 ...
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LOOK AHEAD BALLOUT DIAGRAM CLK AVD WP ...
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provide customers with a migration path to higher densities, as well as the option of stacking more die cka ge pre ce ding diagram s how ...
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ORDERING INFORMATION The order number (Valid Combination) is formed by the following: Am49PDL12 AMD DEVICE NUMBER/DESCRIPTION Am49PDL127BH/Am49PDL129BH Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM 128 Megabit (8 M ...
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MCP DEVICE BUS OPERATIONS This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable ...
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CE#f2 Operation CE#f1 (PDL129 (Notes 1, 2) Active only) (Note 7) Read from L (H) H (L) Active Flash (Note 8) (Note 7) Write to Active L (H) H (L) Flash (Note 8) ...
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Requirements for Reading Array Data To read array data from the outputs, the system must drive the OE# and appropriate CE#f1/CE#f2 (PDL129 only) pins CE#f1 and CE#f2 are the power ...
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Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f1 or CE#f2 (PDL ...
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RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period ...
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Table 5. Am29PDL127H Sector Architecture Bank Sector SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 ...
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Table 5. Am29PDL127H Sector Architecture (Continued) SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 ...
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Table 5. Am29PDL127H Sector Architecture (Continued) SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 ...
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Table 5. Am29PDL127H Sector Architecture (Continued) SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134 SA135 SA136 SA137 SA138 SA139 SA140 SA141 SA142 SA143 SA144 SA145 ...
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Table 5. Am29PDL127H Sector Architecture (Continued) SA159 SA160 SA161 SA162 SA163 SA164 SA165 SA166 SA167 SA168 SA169 SA170 SA171 SA172 SA173 SA174 SA175 SA176 SA177 SA178 SA179 SA180 SA181 SA182 SA183 SA184 SA185 ...
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Table 5. Am29PDL127H Sector Architecture (Continued) SA199 SA200 SA201 SA202 SA203 SA204 SA205 SA206 SA207 SA208 SA209 SA210 SA211 SA212 SA213 SA214 SA215 SA216 SA217 SA218 SA219 SA220 SA221 SA222 SA223 SA224 SA225 ...
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Table 5. Am29PDL127H Sector Architecture (Continued) Bank Sector SA231 SA232 SA233 SA234 SA235 SA236 SA237 SA238 SA239 SA240 SA241 SA242 SA243 SA244 SA245 SA246 SA247 SA248 SA249 SA250 SA251 SA252 SA253 SA254 SA255 ...
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Table 6. Am29PDL129H Sector Architecture Bank Sector CE#f1 SA0 0 SA1 0 SA2 0 SA3 0 SA4 0 SA5 0 SA6 0 SA7 0 SA8 0 SA9 0 SA10 0 SA11 0 SA12 ...
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Table 6. Am29PDL129H Sector Architecture (Continued) SA39 0 SA40 0 SA41 0 SA42 0 SA43 0 SA44 0 SA45 0 SA46 0 SA47 0 SA48 0 SA49 0 SA50 0 SA51 0 SA52 ...
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Table 6. Am29PDL129H Sector Architecture (Continued) SA79 0 SA80 0 SA81 0 SA82 0 SA83 0 SA84 0 SA85 0 SA86 0 SA87 0 SA88 0 SA89 0 SA90 0 SA91 0 SA92 ...
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Table 6. Am29PDL129H Sector Architecture (Continued) SA119 0 SA120 0 SA121 0 SA122 0 SA123 0 SA124 0 SA125 0 SA126 0 SA127 0 SA128 0 SA129 0 SA130 0 SA131 0 SA132 ...
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Table 6. Am29PDL129H Sector Architecture (Continued) SA135 1 SA136 1 SA137 1 SA138 1 SA139 1 SA140 1 SA141 1 SA142 1 SA143 1 SA144 1 SA145 1 SA146 1 SA147 1 SA148 ...
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Table 6. Am29PDL129H Sector Architecture (Continued) SA159 1 SA160 1 SA161 1 SA162 1 SA163 1 SA164 1 SA165 1 SA166 1 SA167 1 SA168 1 SA169 1 SA170 1 SA171 1 SA172 ...
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Table 6. Am29PDL129H Sector Architecture (Continued) SA199 1 SA200 1 SA201 1 SA202 1 SA203 1 SA204 1 SA205 1 SA206 1 SA207 1 SA208 1 SA209 1 SA210 1 SA211 1 SA212 ...
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Table 6. Am29PDL129H Sector Architecture (Continued) SA231 1 SA232 1 SA233 1 SA234 1 SA235 1 SA236 1 SA237 1 SA238 1 SA239 1 SA240 1 SA241 1 SA242 1 SA243 1 SA244 ...
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Table 8. Am29PDL127H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector A22-A12 SA0 00000000000 SA1 00000000001 SA2 00000000010 SA3 00000000011 SA4 00000000100 SA5 00000000101 SA6 00000000110 SA7 00000000111 00000001XXX SA8–SA10 00000010XXX 00000011XXX SA11–SA14 000001XXXXX ...
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Table 9. Am29PDL129H Boot Sector/Sector Block Addresses for Protection/Unprotection Sector CE#f1 CE#f2 A21–A12 SA0 0 1 0000000000 SA1 0 1 0000000001 SA2 0 1 0000000010 SA3 0 1 0000000011 SA4 0 1 0000000100 ...
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SECTOR PROTECTION The Am29PDL127H/Am29PDL129H features several levels of sector protection, which can disable both the program and erase operations in certain sectors or sector groups: Persistent Sector Protection A command sector protection method ...
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not prevent the easy removal of protection when changes are needed. The DYBs maybe set or cleared as often as needed. The PPBs allow for a more static, and difficult to change, level ...
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ences between the Persistent Sector Protection and the Password Sector Protection Mode: When the device is first powered on, or comes out of a reset cycle, the PPB Lock bit set to the ...
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the Password Mode Locking Bit is not set, including Persistent Protection Mode, the PPB Lock Bit is cleared after power-up or hardware reset. The PPB Lock Bit is set by issuing the ...
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START PLSCNT = 1 RESET Wait 4 µs No First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address ...
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Temporary Sector Unprotect This feature allows temporary unprotection of previ- ously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RE- SET# pin During ...
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Increment PLSCNT No PLSCNT = 25? Yes Device Failed Figure 3. PDL127H/129H SecSi Sector Protection Algorithm To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 4. Once ...
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SecSi Sector memory area contents are non-modifi- able. START If data = 00h, RESET# = SecSi Sector unprotected. If data = 01h, SecSi Sector is Wait 1 ...
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Table 11. CFI Query Identification String Addresses Data 10h 0051h 11h 0052h 12h 0059h 13h 0002h 14h 0000h 15h 0040h 16h 0000h 17h 0000h 18h 0000h 19h 0000h 1Ah 0000h Addresses Data 1Bh ...
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Addresses Data 27h 0018h 28h 0001h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0003h 2Dh 0007h 2Eh 0000h 2Fh 0020h 30h 0000h 31h 00FDh 32h 0000h 33h 0000h 34h 0001h 35h 0007h 36h ...
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Table 14. Primary Vendor-Specific Extended Query Addresses Data 40h 0050h 41h 0052h 42h 0049h 43h 0031h 44h 0033h 45h 000Ch 46h 0002h 47h 0001h 48h 0001h 49h 0007h 4Ah 00E7h 4Bh 0000h 4Ch ...
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COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 15 defines the valid register command sequences. Writing incorrect address and data val- ...
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Enter SecSi™ Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, eight word electronic serial num- ber (ESN). The system can access the SecSi Sector ...
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START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data? No Increment Address Last Address? Programming Completed Note: See Table 15 for program command sequence. Figure 5. ...
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DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend ...
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word program command, and all the password data. There is no special addressing order required for pro- gramming the password. Also, when the password is undergoing programming, Simultaneous Operation is disabled. Read operations ...
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cessible for modification. The exact password must be entered in order for the unlocking function to occur. This command cannot be issued any faster than time to prevent a hacker ...
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Command Definitions Tables Table 15. Memory Array Command Definitions Command (Notes) Addr Data Addr Data Addr Data Read ( Reset (6) 1 XXX Manufacturer ID 4 555 Device ID (10) 6 ...
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Table 16. Sector Protection Command Definitions Command (Notes) Addr Data Addr Data Addr Data Reset 1 XXX F0 SecSi Sector Entry 3 555 AA 2AA SecSi Sector Exit 4 555 AA 2AA SecSi ...
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WRITE OPERATION STATUS The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 17 and the following subsections describe the function ...
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RY/BY#: Ready/Busy# The RY/BY dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final ...
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DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or ...
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Status Embedded Program Algorithm Standard Mode Embedded Erase Algorithm Erase Suspended Sector Erase-Suspend- Erase Read Suspend Non-Erase Mode Suspended Sector Erase-Suspend-Program Notes: 1. DQ5 switches to ‘1’ when an Embedded Program or Embedded ...
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ABSOLUTE MAXIMUM RATINGS Storage Temperature Plastic Packages . . . . . . . . . . . . . . . –55°C to +125°C Ambient Temperature with Power Applied ...
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CHARACTERISTICS CMOS Compatible Parameter Parameter Description Symbol I Input Load Current LI I A9, OE#, RESET# Input Load Current LIT I Reset Leakage Current LR I Output Leakage Current ...
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pSRAM DC & OPERATING CHARACTERISTICS Parameter Parameter Description Symbol I Input Leakage Current LI I Output Leakage Current Operating Current CC1 I s Page Access Operating Current CC2 V Output ...
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TEST CONDITIONS Device Under Test C 6.2 kΩ L Note: Diodes are IN3064 or equivalent Figure 11. Test Setup KEY TO SWITCHING WAVEFORMS WAVEFORM Don’t Care, Any Change Permitted 3.0 V 1.5 V ...
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pSRAM AC CHARACTERISTICS CE#1ps Timing Parameter JEDEC Std Description — t CE#1ps Recover Time CCR CE#1ps CE2ps Figure 13. Timing Diagram for Alternating ...
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FLASH AC CHARACTERISTICS Read-Only Operations – Am29PDL127H Parameter JEDEC Std. Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to ...
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FLASH AC CHARACTERISTICS Addresses CE# CE#f2 RH (PDL 129 only) OE# WE# Outputs RESET# RY/BY Addresses A2-A0 Data CE CE#f2 (PDL129 only) OE# Figure 15. Page Read ...
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FLASH AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms) t Ready to Read Mode (See Note) RESET# Pin Low (NOT During Embedded t Ready Algorithms) to Read ...
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FLASH AC CHARACTERISTICS Erase and Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL AS t Address Setup Time to OE# ...
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FLASH AC CHARACTERISTICS Program Command Sequence (last two cycles Addresses 555h CE#f1 or CE#f2 t (PDL129 only) GHWL OE# WE Data RY/BY VCS Notes: 1. ...
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FLASH AC CHARACTERISTICS Erase Command Sequence (last two cycles) Addresses 2AAh CE#f1 or CE#f2 (PDL129 only) t GHWL OE# WE Data RY/BY# t VCS Notes: 1. SADD = ...
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FLASH AC CHARACTERISTICS t WC Valid PA Addresses t AH CE#f1 or CE#f2 (PDL129 only) OE WE# t WPH t Data WE# Controlled Write Cycle Figure 20. Back-to-back Read/Write Cycle Timings ...
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FLASH AC CHARACTERISTICS Addresses CE#f1 or CE#f2 (PDL129 only) t OEH WE# OE Valid Data DQ6/DQ2 RY/BY# Note Valid address; not required for DQ6. Illustration shows first two status ...
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FLASH AC CHARACTERISTICS Temporary Sector Unprotect Parameter JEDEC Std Description t V Rise and Fall Time (See Note) VIDR Rise and Fall Time (See Note) VHH HH RESET# Setup Time ...
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FLASH AC CHARACTERISTICS RESET# SADD, A6, A1, A0 Sector/Sector Block Protect or Unprotect Data 1 µs CE#f1 or CE#f1(PDL129 only) WE# OE# 1. For sector protect ...
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FLASH AC CHARACTERISTICS Alternate CE#f1 Controlled Erase and Program Operations Parameter JEDEC Std. Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address ...
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FLASH AC CHARACTERISTICS 555 for program 2AA for erase Addresses WE# OE# CE# CE#f2 (PDL129 only) Data t RH RESET# RY/BY# Notes: 1. Figure indicates last ...
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pSRAM AC CHARACTERISTICS Read Cycle Parameter Symbol t Read Cycle Time RC t Address Access Time ACC t Chip Enable Access Time CO t Output Enable Access Time OE t Data Byte Control ...
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pSRAM AC CHARACTERISTICS Read Cycle Addresses Addresses A3 to A20 CE#1 CE2 OE# WE# LB#, UB OUT I/ COE ...
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pSRAM AC CHARACTERISTICS Write Cycle Parameter Description Symbol t Write Cycle Time WC t Write Pulse Time WP t Chip Enable to End of Write CW t Data Byte Control to End of ...
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pSRAM AC CHARACTERISTICS Addresses A20 WE# CE CE2 LB#, UB# D High-Z OUT DQ15 to DQ0 D IN (Note 1) DQ15 to DQ0 Notes the ...
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pSRAM AC CHARACTERISTICS Addresses A20 WE# CE CE2 UB#, LB# D High-Z OUT DQ15 to DQ0 D IN DQ15 to DQ0 Notes the device is ...
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ERASE AND PROGRAMMING PERFORMANCE Parameter Sector Erase Time Chip Erase Time Word Program Time Accelerated Word Program Time Chip Program Time (Note 3) Notes: 1. Typical program and erase times assume the following ...
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pSRAM DATA RETENTION Parameter Parameter Description Symbol V V for Data Retention Data Retention Current DR t CE2 Setup Time CS t CE2 Hold Time CH t CE2 Pulse Width ...
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pSRAM ADDRESS SKEW CE#1ps WE# Address Note: If multiple invalid address cycles shorter than t cycle over t is required during that period. RC min CE#1ps WE# Address Note: If multiple invalid address ...
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PHYSICAL DIMENSIONS TLA073—73-Ball Fine-Pitch Grid Array 0.15 C (2X) PIN A1 10 CORNER INDEX MARK TOP VIEW SIDE VIEW 6 b 73X 0. ...
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REVISION SUMMARY Revision A (June 16, 2003) Initial release. Revision A+1 (July 14, 2003) Sector Protection Selecting a Sector Protection Mode: Slightly modified text to improve readability. Pin Description Corrected typo in WP#/ACC ...