am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 19

• Manufacturer Part Number: am49pdl129bh85it
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
• Manufacturer: Meet Spansion Inc.

RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
December 16, 2003
IL
but not within V
SS
±0.3 V, the standby current will
CC4
A D V A N C E
SS
). If RESET# is held
±0.3 V, the device
Am49PDL127BH/Am49PDL129BH
RP
, the
I N F O R M A T I O N
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
tem can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
rithms). The system can read data t
SET# pin returns to V
Refer to the pSRAM AC Characteristics tables for RE-
SET# parameters and to Figure 16 for the timing dia-
gram.
Output Disable Mode
When the OE# input is at V
disabled. The output pins (except for RY/BY#) are
placed in the highest Impedance state
READY
(during Embedded Algorithms). The sys-
READY
IH
.
(not during Embedded Algo-
IH
, output from the device is
RH
after the RE-
17