am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 77
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am49pdl129bh85it
Manufacturer Part Number
am49pdl129bh85it
Description
Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
Manufacturer
Meet Spansion Inc.
Datasheet
1.AM49PDL129BH85IT.pdf
(86 pages)
- Current page: 77 of 86
- Download datasheet (2Mb)
pSRAM AC CHARACTERISTICS
Read Cycle
Notes:
1. t
2. If CE#, LB#, or UB# goes low at the same time or before
December 16, 2003
Addresses
Parameter
A0 to A20
I/O1 to 16
LB#, UB#
the outputs achieve the open circuit condition and are not
referenced to output voltage levels.
WE# goes high, the outputs will remain at high impedance.
Symbol
OD,
t
t
t
t
t
t
t
t
COE
OEE
t
t
ODO
t
t
t
t
t
t
ACC
RC
CO
OE
OD
OH
PM
OH
BA
BE
BD
PC
AA
CE#1
D
t
WE#
ODo
CE2
OE#
OUT
, t
BD
, and t
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Data Byte Control Access Time
Chip Enable Low to Output Active
Output Enable Low to Output Active
Data Byte Control High to Output Active
Chip Enable High to Output High-Z
Output Enable High to Output High-Z
Data Byte Control High to Output High-Z
Output Data Hold from Address Change
Page Mode Time
Page Mode Cycle Time
Page Mode Address Access Time
Page Output Data Hold Time
ODW
are defined as the time at which
High-Z
A D V A N C E
Figure 27. Pseudo SRAM Read Cycle
t
ACC
Am49PDL127BH/Am49PDL129BH
t
COE
Description
t
CO
t
OEE
t
t
BE
OE
t
BA
Indeterminate
I N F O R M A T I O N
t
RC
3. If CE#, LB#, or UB# goes low at the same time or after WE#
goes low, the outputs will remain at high impedance.
Valid Data Out
Max
Max
Max
Max
Max
Max
Max
Max
Min
Min
Min
Min
Min
Min
Min
Min
t
BD
t
ODO
t
OD
t
OH
66
70
70
70
Speed
25
25
10
20
20
20
10
70
30
30
10
0
0
85
85
85
85
Fixed High
High-Z
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
75
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