am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 44

• Manufacturer Part Number: am49pdl129bh85it
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
• Manufacturer: Meet Spansion Inc.

SecSi Sector memory area contents are non-modifi-
able.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes. In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during V
power-up and power-down transitions, or from system
noise.
Low V
When V
cept any write cycles. This protects data during V
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to the read mode. Subsequent
writes are ignored until V
system must provide the proper signals to the control
pins to prevent unintentional writes when V
greater than V
42
CC
Figure 4. SecSi Sector Protect Verify
CC
Write 40h to SecSi
Write Inhibit
Read from SecSi
Sector address
is less than V
Sector address
A1 = 1, A0 = 0
A1 = 1, A0 = 0
Write 60h to
with A6 = 0,
any address
with A6 = 0,
RESET# =
V
Wait 1 µs
LKO
START
IH
or V
.
ID
LKO
CC
, the device does not ac-
is greater than V
Remove V
SecSi Sector is
SecSi Sector is
If data = 00h,
If data = 01h,
from RESET#
Protect Verify
SecSi Sector
unprotected.
Write reset
A D V A N C E
protected.
command
complete
IH
Am49PDL127BH/Am49PDL129BH
or V
ID
LKO
. The
CC
CC
CC
is
I N F O R M A T I O N
Write Pulse “Glitch” Protection
Noise pulses of less than 3 ns (typical) on OE#,
CE#f1, CE#f2 or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
write cycle, CE#f1/CE#f2 and WE# must be a logical
zero while OE# is a logical one.
Power-Up Write Inhibit
If WE# = CE#f1 = V
the device does not accept commands on the rising
edge of WE#. The internal state machine is automati-
cally reset to the read mode on power-up.
COMMON FLASH MEMORY INTERFACE
(CFI)
The Common Flash Interface (CFI) specification out-
lines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-inde-
pendent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the sys-
tem writes the CFI Query command, 98h, to address
55h, any time the device is ready to read array data.
The system can read CFI information at the addresses
given in Tables 11–14. To terminate reading CFI data,
the system must write the reset command. The CFI
Query mode is not accessible when the device is exe-
cuting an Embedded Program or embedded Erase al-
gorithm.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 11–14. The
system must write the reset command to return the
device to reading array data.
For further information, please refer to the CFI Specifi-
cation and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/flash/cfi. Alterna-
tively, contact an AMD representative for copies of
these documents.
IL
, CE#f1 =CE#f2 = V
IL
and OE# = V
IH
or WE# = V
December 16, 2003
IH
during power up,
IH
. To initiate a