am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 86

• Manufacturer Part Number: am49pdl129bh85it
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
• Manufacturer: Meet Spansion Inc.

REVISION SUMMARY
Revision A (June 16, 2003)
Initial release.
Revision A+1 (July 14, 2003)
Sector Protection
Selecting a Sector Protection Mode: Slightly modified
text to improve readability.
Pin Description
Corrected typo in WP#/ACC pin name.
Flash AC Characteristics
Read-only Operation tables (Am29PDL127H and
Am29PDL129H): Changed t
speed option to 25 ns.
SRAM AC Characteristics
Write Cycle table: Added t
tions to table. Changed t
speed option to 65 ns.
Figure 28, Pseudo SRAM Write Cycle—WE# Control:
Added t
Figure 29, Pseudo SRAM Write Cycle–CE#1ps Con-
trol: Added t
Revision A+2 (July 21, 2003)
DC Characteristics
Zero Power Flash: Deleted selection.
Trademarks
Copyright © 2003 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
84
AW
and t
CEH
WEH
to figure.
to figure.
BW
AW
OE
, t
minimum time for the 66
CEH
specification for the 66
A D V A N C E
, and t
Am49PDL127BH/Am49PDL129BH
WEH
specifica-
I N F O R M A T I O N
Revision A+3 (December 16, 2003)
Lookahead Ballout Diagram
Added section and figure.
Figure 1, In-System Sector Protection/ Sector
Unprotection Algorithms
Corrected command sequence to indicate writing 68h
(for protect) and 48h (for verify) with A7–A0 set to
00011010b.
SecSi™ (Secured Silicon) Sector
Flash Memory Region
Customer-Lockable Area: Added sector protection fig-
ure, modified text and changed figure reference in first
bullet from Figure 1 to Figure 3.
Table 16, Sector Protection Command Definitions
Corrected number of cycles for SecSi Protection Bit
Status, PPMLB Status, and SPMLB Status from 4 to 5
cycles. For these command sequences, inserted a
cycle before the final read cycle (RD0).
ESD Immunity
Added section.
December 16, 2003