am49pdl129bh85it Meet Spansion Inc., am49pdl129bh85it Datasheet - Page 3

• Manufacturer Part Number: am49pdl129bh85it
• Description: Stacked Multi-chip Package Mcp Flash Memory And Psram, 128 Megabit 8m ? 16-bit Cmos 3.0 Volt-only, Simultaneous Operation Flash Memory And 32 Mbit 2m ? 16-bit Cmos Pseudo Static Ram With Page Mode
• Manufacturer: Meet Spansion Inc.

Am49PDL127BH/Am49PDL129BH
Stacked Multi-Chip Package (MCP) Flash Memory and pSRAM
128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
and 32 Mbit (2 M x 16-Bit) CMOS Pseudo Static RAM with Page Mode
DISTINCTIVE CHARACTERISTICS
MCP Features
Flash Memory Features
ARCHITECTURAL ADVANTAGES
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Power supply voltage of 2.7 to 3.3 volt
High performance
— Access time as fast as 65 ns initial / 25 ns page
Package
— 73-Ball FBGA
Operating Temperature
— –40°C to +85°C
128 Mbit Page Mode device
— Page size of 8 words: Fast page read access from random
Dual Chip Enable inputs (PDL129 only)
— Two CE# inputs control selection of each half of the memory
Single power supply operation
— Full Voltage range: 2.7 to 3.3 volt read, erase, and program
Simultaneous Read/Write Operation
— Data can be continuously read from one bank while
— Zero latency switching from write to read operations
FlexBank Architecture
— 4 separate banks, with up to two simultaneous operations
— Bank A: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
— Bank B: 48 Mbit (32 Kw x 96)
— Bank C: 48 Mbit (32 Kw x 96)
— Bank D: 16 Mbit (4 Kw x 8 and 32 Kw x 31)
SecSi
— Up to 128 words accessible through a command sequence
— Up to 64 factory-locked words
— Up to 64 customer-lockable words
ADVANCE INFORMATION
locations within the page
space
operations for battery-powered applications
executing erase/program functions in another bank
per device
TM
(Secured Silicon) Sector region
Refer to AMD’s Website (www.amd.com) for the latest information.
PERFORMANCE CHARACTERISTICS
SOFTWARE FEATURES
Both top and bottom boot blocks in one device
Manufactured on 0.13 µm process technology
20-year data retention at 125°C
Minimum 1 million erase cycle guarantee per sector
High Performance
— Page access times as fast as 25 ns
— Random access times as fast as 65 ns
Power consumption (typical values at 10 MHz)
— 45 mA active read current
— 25 mA program/erase current
— 1 µA typical standby mode current
Software command-set compatible with JEDEC 42.4
standard
— Backward compatible with Am29F and Am29LV families
CFI (Common Flash Interface) complaint
— Provides device-specific information to the system, allowing
Erase Suspend / Erase Resume
— Suspends an erase operation to allow read or program
Unlock Bypass Program command
— Reduces overall programming time when issuing multiple
host software to easily reconfigure for different Flash devices
operations in other sectors of same bank
program command sequences
Publication# 30452
Issue Date: December 16, 2003
Rev: A Amendment +3