lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet
lrs1302
Related parts for lrs1302
lrs1302 Summary of contents
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... P S RODUCT PECIFICATIONS LRS1302 Stacked Chip 8M Flash and 1M SRAM Issue Date: June 11, 1999 ® (Model No.: LRS13023) Spec No.: EL116039 Integrated Circuits Group ...
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... Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. l Please direct all queries regarding the products covered herein to a sales representative of the company. LRS13023 application areas, be sure ...
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... SHARP l.Description The LRS1302 is a combination memory organized as bit static RAM in one package. memory and 131,072X8 It is fabricated using silicon-gate CMOS process technology. Features OAccess Time Flashmemoryaccesstime SRAM access time OOpemtingcurrent Flash memory Read Byte write Block erase SRAM operatin% ostandbycurrent ...
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... SHARP l.Description The LRS1302 is a combination memory organized as memory and bit static RAM in one package. 131,072X8 It is fabricated using silicon-gate CMOS process technology. OAccess Time Flashmemoryaccesstime SRAM access time OOpemtingcment Flash memory Read Byte write Block erase SRAM Operating ostandbycurrent Flash memory Sk4M (Total standby current is the summation of Flash memory’ ...
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... The power supply is needed to be designed carefully because one of the SRAM and the Flash Memory is in standby mode when the other is active. A careful decoupling of power supplies is necessary between SRAM and Flash Memory. Note peak current caused by transition of control signals. The contents described in Part 1 take first priority over Part 2 and Part 3. LRS13023 OF FLASH MEMORY AND SRAM and S-E should be LOW simultaneously ...
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... I > S-TE / > S-FE > s-m ; The contents described in Part 1 take first priority over Part 2 and Part 3. LRS13023 S-a S-m S-m Address Mode Flash read Flash read Flash write SRAM read sR4M read SRAM write Standby Deep power down High-Z level at the samc,limc. When F-V&V,,.,.,, memory contents can be read, but not altered ...
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... This voltage is applicable toi@ Pin only the lower one of S-V, 8.Pin Capacitance Parameter Symbol Input capacitance Gi I/O capacitance CIA3 Note) * 16. Sampled but not 100% tested The contents described in Part 1 take first priority over Part 2 and Part 3. LRS13023 CT,= -40°C to +85”c Min. Max. TYP. 2.7 3.0 3.6 2.2 V,,+O.3 (*15) 0.4 -0.3 (*13: 11 ...
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... Read Status Register Command.. 4.4 Clear Status Register Command ............................................ 4.5 Block Erase Command 4.6 Byte Write Command .............................................. 4.7 Block Erase Suspend Command 4.8 Byte Write Suspend Command.. 4.9 Set Block and Master Lock-Bit Commands LRS13023 Part2 Flash memory CONTENTS PAGE 4.10 Clear Block Lock-Bits Command DESIGN CONSIDERATIONS 9 5 ...
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... Read Status Register Command.. 4.4 Clear Status Register Command ............................................ 4.5 Block Erase Command .............................................. 4.6 Byte Write Command 4.7 Block Erase Suspend Command 4.8 Byte Write Suspend Command.. 4.9 Set Block and Master Lock-Bit Commands LRS13023 Part2 Flash memory CONTENTS PAGE 4.10 Clear Block Lock-Bits Command DESIGN 9 5.1 Three-Line 5 ...
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... SmartVoltage Technology *Enhanced Suspend Capabilities Jn-System Block Locking 30th devices share a compatible, status register, and oftware command set. These similarities clean upgrade from the 28FOO8SA to LRS1302. When upgrading important to note iifferences: -Because of new feature support, have different device codes. software optimization. ...
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... WSM’s erase, byte write, or lock-bit configuration finished. The access time is 130 ns (tAvQv) over the commercial temperature range (-40°C to +BS’C) and V,, voltage range of 2.7V-3.6V LRS13023 of bits, The Automatic substantially to lock in static mode (addresses not switching). gates configuration When a standby mode is enabled ...
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... DC Characteristics) byte write and lock-bit GND SUPPLY GROUND: Do not float any ground rote: V,-, , and WE mean F-V,,, LRS13023 Table 2. Pin Descriptions Name and Function Inputs for addresses during latched during a write cycle. Inputs data and commands memory ...
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... SHARI= 2 PRINCIPLES OF OPERATION The LRS1302 SmartVoltage Flash memory on-chip WSM to manage block erase, byte write, and lock-bit configuration functions. It allows TTL-level control inputs, fixed power supplies block erasure, byte write, and lock-bit and minimal processor overhead interface timings. After initial device power-up ...
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... VI, and m must be at V,, or V,,. llustrates a read cycle. 1.2 Output Disable Mith 0lY at a logic-high level (Vt,), the device outputs Ire disabled. Output pins I/0,-1/0, high-impedance state. LRS13023 3.3 Standby logic-high even when high standby functions are power consumption. a high-impedance deselected during protection from ...
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... Future Implementation oooo4 Master Lock Configuration oooo3 ------------------------------------. Block 0 Lock Configuration moo2 ~~~~~~~~----__-__---________________( ooml Device Code --------_-__________----------------. Manufacturer Code Figure 3. Device Identifier Code Memory LRS13023 3.6 Write Writing outputs the block lock device data and identifier and the master inspection V,--=Vccl 3). Using the controls configuration ...
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... Block erase, byte write, or lock-bit configuration Vcc=VccIU~=O results and should not be attempted. 6. Refer to Table 4 for valid h during a write operation. 7. Don’t use the timing both m and m LRS13023 memory contents can be read, but not altered. or VP,, for VP,. See DC Characteristics current. ...
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... If the master lock-bit is set, RP must be at V,, simultaneously clears all block lock-bits. -. done while RR 1s Vl,. 9. Commands other than those shown above are reserved by SHARP not be used. LRS13023 1 Definitions(9) Table 4. Commanc - - ___. Fist Bus Cycle Ope# ) Addrc2) 1 DataQ) Notes Write ...
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... Locked ,Reserved for Future Use IOTE selects the specific block lock configuration to be read. See Figure’3 for the device code memory map. LRS13023 4.3 Read Status Register The status register to read array block erase, byte write, by writing the complete enabled for successfully ...
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... In the absence of this high voltage, nemory contents are protected against byte writes. If >yte write is attempted while VpplVppm, LRS13023 status register bit register bits SR3 and SR4 will be set to “1”. Successful byte write erase error is lock-bit be cleared or, if set, that i@=V,. is attempted actions ...
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... Set Block Lock-Bit command and V, see Table 6 for a summary of hardware and software write protection options. LRS13023 Set block lock-bit and master lock-bit are executed by a two-cycle command lock-bit setup along with appropriate allows byte write address is written ...
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... Lock-Bit 1 X Set Master X X Lock-Bit Clear Block X 0 Lock-Bits 1 X LRS13023 accidentally command SR.4 and SR5 being set to “1”. Also, a reliable via the block lock-bits With the master Vcc=VccI If the master operation SR.5 will be set to “1”. In the absence of this high ...
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... Byte Write Suspended 0 = Byte Write in Progress/Completed SR.l = DEVICE PROTECT STATUS 1 = Master Lock-Bit, Block Lock-Bit Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS LRS13023 Table 7. Status Register Definition ( BWSLBS ( VPRS 4 3 NOTES: Check SR.7 to determine lock-bit configuration SR6-0 are invalid while SR.7=“0”. If both SR.5 and SR.4 are “1”s after a block erase or ...
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... SHARP Suspmd Check If Deeired FULL STATUS CHECK PROCEDURE Read Status Beg&r IhtaCSee Above) Block EmseSucceseful Figure 4. Automated LRS13023 Read I Black Repeat for subsequent block erasores. Full ,tailhls check can be done after each block bbck erasuree. Write FFH after Ibe kut operation ...
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... SHARI= Write 4OH or 10H Add- Wrih Byte Data and Addrerr FULLZTATIJS CHECK PROCEDURE DataGee Above) Device Protect Error Figure 5. Automated LRS13023 Bus Command Opation Data=Data Write Byte write Addr=LocaMon I status Rnd I Repeat for subsequent byte writes.. SR full stahn check can be done after each byte write. ...
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... I Figure 6. Block Erase Suspend/Resume LRS13023 checksR7 1dvsMRcPdy O=WSM Busy I Emm Dala=DoH Wrik Resume I AddrrX I Flowchart 24 I ...
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Wrib Wrik I Rd Figure 7. Byte Write Suspend/Resume Byte write Dah=BOH AddrX &Pd Sbhw Rrgister Dab I Add-X mta=FFH -AmY Addr=X I Red Amy locatiom othrr than that being wrhn. Flowchart ...
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... SHARP . .,,,I - Block/Devke Addraa WriteOlHFtH. Block/Device Add= Check if Desired FULLSTATlJSCHECKPROCEUJRE Set Luck-Bit ’ LRS13023 &pent for subsquent Pull ,btus check an be don or after P aqucm of lock-bit Write ITH after the last lock-bit / read array made. SR55R4,SR3andSRlareoniyclearedbythe command In cases where Emw If aror is detected, dear Figure 8 ...
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... Write 60H Wrttc WH Sbtua RLghbr 3 0 sR.7. 1 FULL STATUS CHECK PROCEDURE Figure 9. Clear Block Lock-Bits LRS13023 aear Bbck Dh=WH Add-X Luck-Bib Confirm Write FFH after tk Clear Block Lock-Bib opwatton ptw devke in mad array mode. Ckk l=Ddce i&V,“, Check SR4.5 Both I=commad SequmctErmr ...
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... Transient current magnitudes depend on the device LRS13023 outputs’ control and proper decoupling suppress transient voltage peaks. Each device shouId have a 0.1 uF ceramic capacitor connected between its V,, and GND and between its V,, and GND ...
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... V,,) powers-up first. Internal ‘esets the GUI to read array mode at power-up. LRS13023 A system designer must guard against spurious for V,eoltages both WE and m must be low for a comman configuration are of a valid VP= driving either to VIH will inhibit ...
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... Current . . . . . . . . . . . . . . . . . . . . . . . . . . lOOmA( Operating Conditions Symbol Parameter T* Operating Temperature V,,, V,, Supply Voltage (2.7V-3.6V) JOTE: . FLASH Erase/Write (TA=O to 85°C) LRS13023 *WARNING: Maximum These are stress ratings “Operating extended exposure beyond may affect device reliability. NOTES: 1. Operating defined by this specification. 2. All specified Minimum and -0.2V on Vc- and V, this level ~2011s ...
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... Input rise and fall times (10% to 90%) cl0 ns. Figure 10. Transient 13 lN914 CL Includes Jig Capacitance Figure 11. Transient Equivalent Circuit LRS13023 and O.OV for a Logic “0.” Input timing begins, and output timing ends, at 1.35V. InputjOutput Reference Waveform Test Configuration Test Configuration Vo=2.7V-3.6V -c Testing Load for V,-=2.7V-3.6V ...
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... Erase Suspend Current VP, Standby or Read bPs Current Ipp* Deep Power-Down VPP IlTD Current VP, Byte Write or 4TW SetLock-Bit Current VP, Block Erase orClear IPPE Lock-Bit Current VP, Byte Write or Block IPPWS Erase Suspend Current PPFS LRS13023 DC Characteristics Vcc=2.7V-3.6V Notes Typ Max unit 100 1 ...
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... Power Savings @F’S) reduces typical ~C-J to 3mA at 3.3V V,- in static operation. 5. CMOS inputs are either V,-c- +0.2V or GNDk0.2V. 6. Sampled, not 100% tested. 7. Master lock-bit set operations are inhibited when the master lock-bit is set and Rp=V,. block-lock bit is set and P=VIH connection supp allowed for a Maximum LRS13023 DC Characteristics (Continued 0.85 V,, V Vcc -0.4 1.5 V ...
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... OE to Outo; 1tinLowz Cm-Ii Output in High Z Output Hold from Address Whichever Occurs First NOTES: 1. See AC Input/Output Reference Waveform 2. m may be delayed up to tELQV-kLQV 3. Sampled, not 100% tested. LRS13023 OPERATIONS(‘) Vo=2.7V-3.6V, TA=-400C to +8S”C 1 Notes Change, ...
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... SHARI= Device Address Selection , .DDRESS~A) , tAVEL- HIGH Z VOL I, vcc tPHOV 4 VIH I -E(P) VIL Figure 12. AC Waveform for Read LRS13023 Data Valid ----------- Address Stable -__----__ ::::::::::y:::y%{ Valid Output tavnv -----------7 c ------------ Operations HIGH z ...
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... Refer to AC Characteristics 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid A, and b ( and if necessary TRf should be held at V should be held at V,,, write, or lock-bit configuration success (SR1/3/4/5=0). LRS13023 Vo=27V-3.6V, T,=O’C to +85”C Notes for read-only operations. ...
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... NOTES: 1. VCC power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Figure 13. AC Waveform LRS13023 tvwH c4VAV I hHcL I I for T& ...
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... Sampled, not 100% tested. 3. Refer to Table 4 for valid AIN and DIN for block erase, byte write, or lock-bit configuration. ( and if necessary m should be held un$l determination,of 4. VP, should be held at VP,, write, or lock-bit configuration success (SR1/3/4/5=0). LRS13023 WRITES(‘) V PP- -27V-3.6V. TA =O”C to +85”C a longer WE tir& ...
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... VIII NOTES: 1. VCC power-up and standby. 2. Write block erase or byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command. Figure 14. Alternate LRS13023 Waveform for CE-Controlled ...
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... RP Pulse Low Time :PLPH ( tied to Vcc, this specification applicable) V,, 2. High YPH lOTES: . When the device power-up, holding and also has been in stable there. LRS13023 bLPH (AlReset During Read Array Mode, Block Erase, Byte Write or Lock-Bit Configuration tVPH - I 7- ...
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... BLOCK ERASE, BYTE WRlTE AND LOCK-BIT NOTES: 1. Typical values measured at TA- -+2S”C and nominal to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. LRS13023 CONFIGURATION PEWORMANCE(3) voltages. Assumes corresponding 41 I lock-bits are not set. Subject ...
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... Timing Chart ..................................................................................................... LRS13023 Part3SRAM CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Access Time current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Standby current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data retention current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..s...... Single power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L Fully static operation Three-state output Not designed or mted as tadiation hardened N-type bulk silicon LRS13023 bit which provides ns(M mA(Max. ~a~200ns) 30 @(Max.) 0.7 pA(Typ. V,,=3V, 2.7V to 3.6V -40°C lo +85”c 43 T,=25”c) ...
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... SHARP 2.Trut.h Table (CE, OE and %% mean S-B, (X=Don’t Care, L.=Low, H=High) 3.Block Diagram (V, means S-V,-J k-- Row 1 r’ LRS13023 S-zand S-a respectively.) Memory -Y (512X2048) Y Circuit 8 Column Decolde$ Control 44 ...
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... EC1 cE=V, ,V,,=V, Operating supply kc2 i%10.2V current V,=O.2V or V,-0.2V * v,-0.2v Standby current , I Sal cE=V, output V, h=2.OmA voltage V , I,,=2.omA aI Note $4. T,=25”c, Ve3.OV LRS13023 Ratings Symbol to +4.6 -0.2 VCC -0.3 (*2) to v&o.3 YN ” Topr -4) to +I35 +125 -65 Min. TYP. 2.7 3.0 2.2 -0.3 (*3) (T,= -40°C to +85”c , V,--= Conditions to v, ...
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... Input and Output timing Ref. level output Note * 5. Including scope and jig capacitance. Read cvcie Write cycle Note * 6. Active output to High impedance and High impedance to output active tests specified for a f2OOmV from steady state levels into the test load. LRS13023. 0.4v to 2.4V 5ns I 1.5v I 1m+cL~1oopF) CT,= 40° ...
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... SHARP 8.Data Retention Characteristics Symbol Parameter - V c(DR Data Retention CE _2 vc,p,-0.2v supply voltage Gn]R v-=3v - Data Retention CE ZVnDR-0.2V supply current Chip enable kDR setup time Chip enable tR hold time -c LRS13023 CL= Conditions Min. 2.0 1 T,=25” -40°C to +85’c ) Typ. Max. Unit 3.6 v 0.7 1 ClA ms ms ...
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... SHARP 9.Timing Chart Read cycle timing chart (*7) < OE Note * high for Read cycle. Write cycle timing chart (?% Controlled) < \&I-> LRS13023 kC > t-l 43 ttw (*g) td*8) ;&, > \( \\\\ 1111 (*11) > ...
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... If CE goes low simultaneously with Wl? going low or after WE going low, the outputs remain in high impedance state goes high simultaneously with WE going high or before WE going high, the outputs remain in high impedance state. -_ LRS13023 < (* going low and WE going low. ...
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... SHARP LRS13023 ...
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... Conditions for removal of residual (1) Ultrasonic washing power (2) Washing time (3) Solvent temperature LRS13023 SHARP Indicates the product in the WWth week of 19YY. - Denotes the production Denotes the production (Lower two digits the country of origin. ...
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... Top Covering *Peeling strength must meet the following 1) Peeling angle at 165” to 180” 2) Peeling speed at 300mm/min. 3) Peeling strength at 0.2 to 0.7N(ZO LRS13023 Taping Specification) taping specificat based on those set forth is made of conductive plastic. with IC packages and covered them. Tape Size tape sizes, ...
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... This dry packing is designed surface mount packages. the storage and opening LRS13023 side) at the leading edge of the embossed edge of the embossed carrier tape exceeding 3Omm in length. edges of the embossed carrier not filled with IC packages), in the embossed carrier be as listed below ...
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... The recommended conditions hours at 150°C. Note that the embossed carrier at the above temperature. (3) Storage after baking After baking ICs, store 5-3.(l). LRS13023 shown below before opening the dry packing : 5-40x : 80 less prepare a working table strap. the dry packing to prevent ...
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... SHARf= LRS1302 YYWW 12. 4*0.3 DETAIL LEAD FINISH TSOP40-P-0813/0.4 q&E UNIT RAWING NO. i AA2017 LRS13023 I xxx - SEE DETAIL A A PLATING NOTE Plastic body dimensions ; burr of resin. ‘ not include ...
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... SHARP EMBOSS 1 IC TAPING DlRECTlON 1 [LEADER SIDE MD !3D SIDE OF TAF'E ] ADHE$Ig ;;;E(?APER CARRIER TAPE ; : 500mm MIN --_ EMBOSS TAPING TYPE lAME i 4-m DRAWING NO. i UNIT i cv522 LRS13023 TAPING TYPE DIRECTION OF TAPE THE DRAWING FILLED EMBoss(WITH IC PACKAGE) I Bit* NCVE ...
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... SHARP EC28-0813TSPTS YE / @AWING NO. j CV674 UNIT 1 mm LRS13023 fr#i% NOTE 57 ...
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... SHARP AME i CARRIER TAPING NOTE REEL FOR EMBOSS ll?z j UNIT j mm DRAWING NO. j CV755 LRS13023 ...
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... SHARP EXTERNAL APPEARANCE OF PACKING #if% %Rj NAME i CASE FOR EMBOSS CARRIER TAPING ( 4w f DRAWING NO. 1 BJ279 ) UNIT LRS13023 345X345X55 CASE SIZE : NOTE (mm> ...