lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 14

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

2 PRINCIPLES
The LRS1302 SmartVoltage
on-chip
lock-bit
TTL-level
block erasure, byte write, and lock-bit
and
interface timings.
After
power-down
defaults
memory
output disable operations.
Status register
through
voltage on V,, enables successful block erasure, byte
writing,
associated with altering memory
byte
identifier
through
Commands
write timings.
WSM, which controls the block erase, byte write, and
lock-bit
regulated
internal
and data are internally
Writing
accesses the identifier
data.
Interface
block erase, byte write, and lock-bit
be stored in any block. This code is copied
executed
updates. After successful completion,
possible
suspend allows system software
erase to read or write data from any other block. Byte
write suspend allows system software
byte write to read data from any other flash memory
array location.
SHARI=
minimal
initial
write,
verification,
the appropriate
WSM to manage block erase, byte write, and
configuration
the status register.
to read array mode. Manipulation
the CUI independent
configuration.
via the Read Array
control
software that initiates
and
codes-are
from
control inputs, fixed power supplies
by the WSM,
are written using standard
device power-up
mode (see Bus Operations),
The CUI contents serve as input
Lock-bit
lock-bit
processor
and identifier
OF OPERATION
system
pins allow array read, standby,
accessed via the CUI and verified
and margining
codes, or outputs
functions.
configuration.
The internal
command
RAM
configuration,
overhead
including
latch
Flash memory
of the VP, voltage. High
command.
codes can be accessed
during
or return
and polls progress of
during
contents-block
It allows
to suspend
outputs
of data. Addresses
configuration
pulse repetition,
with
reads are again
microprocessor
algorithms
flash memory
configuration,
All
status register
to suspend
write
status,
Block erase
includes
from
array data,
of external
RAM-Like
the device
for: 100%
functions
a block
during
to and
cycles.
LRS13023
to the
erase,
deep
and
and
can
are
an
a
2.1 Data Protection
Depending
may choose to make the V,, power supply
writes,
hardwired
design practice
processor-memory
(available
or lock-bit
SFFFF
SFFFF
OFFFF
Aoooo
9FFFF
7FFFF
6FFFF
2Izzz
9oMw)
8oooO
7owo
t5wlo
mm
ooom
only
to V,,,.
on the application,
I
I
I
I
Figure 2. Memory
and encourages
when
interface.
configurations
The device accommodates
64Kbyte
64-Kbyte Block
64Kbyte
64Kbyte
64Kbyte
memory
Block
Block
Block
Block
the system designer
optimization
Map
block
are required)
erases, byte
15 I
10 I
4 1
0
l/
switchable
of the
either
12
or