lrs1302 Sharp Microelectronics of the Americas, lrs1302 Datasheet - Page 18

• Manufacturer Part Number: lrs1302
• Description: 8m Flash And 1m Sram
• Manufacturer: Sharp Microelectronics of the Americas

NOTES:
1. BUS operations
2. X=Any valid address within the device.
3. SRD=Data
4. Following
5. If the block is locked, i?i? must be at V,,
6. Either 40H or 10H are recognized
7. If the master lock-bit is set, m must be at V,,
8. If the master lock-bit is set, RP must be at V,,
9. Commands
Suspend
Read Array/Reset
Read Identifier
Read Status Register
Clear Status Register
Block Erase
Byte Write
Block Erase and Byte Write
Block Erase and Byte Write
Resume
Set Block Lock-Bit
Set Master Lock-Bit
Clear Block Lock-Bits
WA=Address
IA=Identifier
BA=Address
WD=Data
ID=Data
master lock codes. See Section 4.2 for read identifier
erase or byte write to a locked block while m is VII+
If the master lock-bit is not set, a biock lock-bit can be set while i?is is V,,.
simultaneously
done while RR 1s Vl,.
not be used.
SHARI=
Command
read from identifier
the Read Identifier
to be written at location WA. Data is latched on the rising edge of WE or CE (whichever
read from status register. See Table 7 for a description
-.
other than those shown above are reserved by SHARP
Codes
within the block being erased or locked.
Code Address: see Figure 3.
of memory
are defined in Table 3.
clears all block lock-bits.
location
RIW
Req’d .
codes.
Codes command,
f-vr1c.c
22
1
2
1
2
2
1
2
2
2
1
by the WSM as the byte write setup.
to be written.
I
Table 4. Commanc
Notes
”
If the master lock-bit is not set, the Clear Block Lock-Bits command
56
to enable block erase or byte write operations.
4
5
5
5
7
7
8
LRS13023
I
to set a block lock-bit. RP must be at V,,
to clear block lock-bits. The clear block lock-bits operation
read operations
Ope#
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
code data.
Fist Bus Cycle
) Addrc2) 1 DataQ)
I
1 Definitions(9)
- - ___._. ~_ _
WA
BA
BA
X
X
X
_.
X
X
X
X
X
access manufacturer,
of the status register bits.
for future device implementa
I
DOH
----
FFH
BOH
90H
70H
5UH
20H
60H
60H
60H
----
40H
10H
or
I
Oper(l)
Write
Write
Write
Write
Write
Read.
Read
device, block lock, and
Second Bus Cycle
Attempts
to set the master lock-bit.
1 Addrt2)
I
I
WA
BA
BA
IA
X
X
X
lions and should
to issue a block
goes high first).
1 Datac3)
I
I
SRD
DOH
DOH
OlH
FlH
WD
ID
can be
I
16