mt18vddt12872ag-335 Micron Semiconductor Products, mt18vddt12872ag-335 Datasheet
mt18vddt12872ag-335
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mt18vddt12872ag-335 Summary of contents
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... DDR SDRAM UNBUFFERED DIMM Features • 184-pin dual in-line memory module (DIMM) • Fast data transfer rates: PC2100 or PC2700 • Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components • Supports ECC error detection and correction • 256MB (32 Meg x 72), 512MB (64 Meg x 72), 1GB (128 Meg x 72) 2GB (256 Meg x 72) • ...
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... All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDT6472AG-265B1. 2. Contact Micron for product availability. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, DR) MODULE CONFIGURATION MODULE DENSITY BANDWIDTH 256MB 32 Meg x 72 2.7 GB/s 256MB 32 Meg ...
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Table 3: Pin Assignment (184-Pin DIMM Front PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL DQ17 47 REF 2 DQ0 25 DQS2 DQ1 DQS0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information PIN NUMBERS 63, 65, 154 WE#, CAS#, RAS# 16, 17, 75, 76, 137, 138 CK0, CK0#, CK1, CK1#, ...
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... TYPE Input/ Data I/Os: Data bus. Output SCL Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. SA0–SA2 Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. SDA Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to ...
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... CKE1 3 WE# NOTE: 1. All resistor values are 22 unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, DR) ...
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... I/O pins. A single read or write access for the DDR SDRAM module effec- tively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corre- sponding n-bit wide, one-half-clock-cycle data trans- fers at the I/O pins ...
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... A11 A10 Operating Mode * M13 and M12 (BA0 and BA1) must be “0, 0” to select the base mode register (vs. the extended mode register). 512MB and 1GB Modules BA1 A8 BA0 A12 A11 A10 Operating Mode * M14 and M13 (BA0 and BA1) must be “ ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES WITHIN LENGTH ADDRESS TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1 ...
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... DDR SDRAM UDIMM Figure 6: Extended Mode Register Definition Diagram 256MB Module BA1 BA0 A10 A8 A11 Operating Mode 512MB and 1GB Modules BA1 BA0 A10 A8 A12 A11 Operating Mode 2GB Module ...
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Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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... Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module banks Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN ...
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... Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN ...
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... Address and control inputs change only during Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN ...
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... Address and control inputs change only during Active READ, or WRITE commands NOTE: a: Value calculated as one module rank in this operating condition, and all other module ranks Value calculated reflects all module ranks in this operating condition. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN ...
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Table 16: Capacitance Note: 11; notes appear on pages 19–22 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S#, CKE Input Capacitance: CK, CK# Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating ...
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Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 8, 12–15, 29, 49; notes appear on pages 19–22; 0°C AC CHARACTERISTICS PARAMETER Address and control input setup time (slow slew rate) Address and Control ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM control- ler greater than eight refresh cycles is not allowed. 22. The valid data window is derived by ...
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READs and WRITEs with auto precharge are not t allowed to be issued until RAS (MIN) can be satis- fied prior to the internal precharge command being issued. 32. Any positive glitch must be less than 1/3 of the ...
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... Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW defined as a steady state logic HIGH or LOW ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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... NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across the module when installed in a system. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 12, Data Validity, and Figure ...
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Table 18: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 19: EEPROM Operating Modes MODE RW BIT Current Address Read Random Address Read Sequential ...
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Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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... Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels 9 t SDRAM Cycle Time, CK CAS Latency = 2.5 (see note 1) 10 SDRAM Access from Clock, CAS Latency = 2.5 11 ...
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... SPD Revision 63 Checksum for Bytes 0–62 64 Manufacturer’s JEDEC ID Code 65-71 Manufacturer’s JEDEC ID Code 72 Manufacturing Location 73-90 Module Part Number (ASCII) 91 PCB Identification Code 92 Identification Code (Continued) 93 Year of Manufacture in BCD pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, DR) ...
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... The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, DR) 184-PIN DDR SDRAM UDIMM ENTRY (VERSION) ...
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... Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 Number of Column Addresses on Assembly 5 Number of Physical Ranks on DIMM 6 Module Data Width 7 Module Data Width (Continued) 8 Module Voltage Interface Levels 9 t SDRAM Cycle Time, CK, CAS Latency = 2.5 (see note 1) 10 SDRAM Access from Clock, CAS Latency = 2.5 ...
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... The value of RP, RCD and RAP for -335 modules indicated as 18ns to align with industry specifications; actual DDR SDRAM device specification is 15ns. pdf: 09005aef80814e61, source: 09005aef807f8acb DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN 256MB, 512MB, 1GB, 2GB (x72, ECC, DR) 184-PIN DDR SDRAM UDIMM ENTRY (VERSION) ...
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Figure 16: 184-PIN DIMM Dimensions 0.079 (2.00) R (4X 0.098 (2.50) D (2X) 0.091 (2.30) TYP. PIN 1 0.091 (2.30) 0.050 (1.27) TYP. TYP. U19 U10 U11 PIN 184 1.95 (49.53) NOTE: All dimensions in inches (millimeters); Data ...