mt18vddt12872ag-335 Micron Semiconductor Products, mt18vddt12872ag-335 Datasheet - Page 21

• Manufacturer Part Number: mt18vddt12872ag-335
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

pdf: 09005aef80814e61, source: 09005aef807f8acb
DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN
31. READs and WRITEs with auto precharge are not
32. Any positive glitch must be less than 1/3 of the
33. Normal Output Drive Curves:
Figure 8: Pull-Down Characteristics
allowed to be issued until
fied prior to the internal precharge command
being issued.
clock and not more than +400mV or 2.9 volts,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive. How-
ever, the DC average cannot be below 2.3V mini-
mum.
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
d. The variation in driver pull-up current within
e. The full variation in the ratio of the maximum
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 8, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
9, Pull-Up Characteristics.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
t
RAS (MIN) can be satis-
256MB, 512MB, 1GB, 2GB (x72, ECC, DR)
21
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
41. For -335, -262, -26A, and -265 speed grades, I
42. Random addressing changing and 50 percent of
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
is specified to be 35mA per DDR SDRAM device at
100 MHz.
data changing at every transfer.
Figure 9: Pull-Up Characteristics
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
DD
RPST), or begins driving (
TT
184-PIN DDR SDRAM UDIMM
(MIN) = -1.5V for a pulse width
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
overshoot: V
and V
may be 1.35V maximum during power up,
t
of series resistance is used between the V
DQSCK (MIN) +
DD
DD
DD
level and the referenced test load. In
/V
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0V, provided a minimum of
IH
(MAX) = V
t
RPRE (MAX) condition.
t
RPRE begin point are not
DD
©2004 Micron Technology, Inc. All rights reserved.
DD
t
Q, V
t
LZ (MIN) will prevail
RPRE).
+ 0.3V. Alternatively,
TT
t
DQSCK (MAX) +
, and V
DD
IL
Q+1.5V for a
undershoot:
3ns and the
REF
DD
must
3N
TT