mt18vddt12872ag-335 Micron Semiconductor Products, mt18vddt12872ag-335 Datasheet - Page 13

• Manufacturer Part Number: mt18vddt12872ag-335
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 12: I
DDR SDRAM components only
Notes: 1–5, 8, 12–15, 48; notes appear on pages 19–22; 0°C
pdf: 09005aef80814e61, source: 09005aef807f8acb
DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN
PARAMETER/CONDITION
NOTE:
OPERATING CURRENT: One device bank; Active-Precharge;
t
changing once per clock cyle; Address and control inputs
changing once every two clock cycles
OPERATING CURRENT: One device bank; Active -Read Precharge;
Burst = 2;
and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;
t
once per clock cycle. V
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank
active; Power-down mode;
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge;
DM and DQS inputs changing twice per clock cycle; Address and
other control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle;
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once
per clock cycle;
changing twice per clock cycle
AUTO REFRESH CURRENT
SELF REFRESH CURRENT: CKE
OPERATING CURRENT: Four device bank interleaving READs (BL =
4) with auto precharge,
and control inputs change only during Active READ, or WRITE
commands
RC =
CK MIN; CKE = HIGH; Address and other control inputs changing
a: Value calculated as one module rank in this operating condition, and all other module banks in I
b: Value calculated reflects all module ranks in this operating condition.
t
t
RC (MIN);
CK =
t
RC =
t
CK (MIN); I
t
t
DD
CK =
RC (MIN);
t
CK =
Specifications and Conditions – 256MB
t
CK (MIN); DQ, DM, and DQS inputs
IN
t
CK (MIN); DQ, DM and DQS inputs
OUT
t
t
= V
RC =
RC =
t
CK =
t
t
CK =
CK =
= 0mA
REF
t
t
RC (MIN);
RAS (MAX);
t
0.2V
for DQ, DQS, and DM
t
CK (MIN); CKE = (LOW)
CK (MIN); CKE = LOW
t
CK (MIN); I
t
CK =
t
CK =
OUT
t
t
Standard
Low Power
REFC =
REFC = 15.625µs
t
CK (MIN); Address
= 0mA; Address
t
CK (MIN); DQ,
256MB, 512MB, 1GB, 2GB (x72, ECC, DR)
t
RFC (MIN)
t
13
CK =
T
A
+70°C; V
I
I
I
I
I
I
I
I
SYM
DD4W
I
I
DD3N
I
DD5A
I
DD6A
I
DD2P
DD2F
DD3P
DD4R
DD5
DD6
DD0
DD1
DD7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
b
b
a
a
a
b
b
b
a
b
b
b
a
DD
= V
1,152
1,242
1,287
1,287
4,770
3,222
-335
810
450
900
54
90
27
23
DD
Q = +2.5V ±0.2V
MAX
1,017
1,107
1,197
1,152
3,960
2,997
-262
810
450
900
54
45
27
23
©2004 Micron Technology, Inc. All rights reserved.
-26A/
1,107
1,152
1,107
3,960
2,952
-265
972
720
360
810
54
45
18
23
DD
2
P
(CKE LOW) mode.
UNITS
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
NOTES
21, 28,
21, 28,
20, 42
20, 42
20, 42
24, 44
20, 43
44
45
44
20
44
9
9