mt18vddt12872ag-335 Micron Semiconductor Products, mt18vddt12872ag-335 Datasheet - Page 9

• Manufacturer Part Number: mt18vddt12872ag-335
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Table 6:
NOTE:
Table 7:
pdf: 09005aef80814e61, source: 09005aef807f8acb
DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN
LENGTH
1. For a burst length of two, A1-Ai select the two-data-
2. For a burst length of four, A2-Ai select the four-data-
3. For a burst length of eight, A3-Ai select the eight-data-
4. Whenever a boundary of the block is reached within a
5. i = 9 (256MB, 512MB)
BURST
element block; A0 selects the first access within the
block.
element block; A0-A1 select the first access within the
block.
element block; A0-A2 select the first access within the
block.
given sequence above, the following access wraps
within the block.
i = 9, 11 (1GB, 2GB)
2
4
8
SPEED
-26A
-335
-262
-265
A2
0
0
0
0
1
1
1
1
STARTING
ADDRESS
COLUMN
Burst Definition Table
CAS Latency (CL) Table
A1 A0
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
75
75
75
75
CLOCK FREQUENCY (MHZ)
ALLOWABLE OPERATING
CL = 2
ORDER OF ACCESSES WITHIN
0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
SEQUENTIAL
f
f
f
f
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
133
133
133
100
0-1
1-0
A BURST
75
75
75
75
INTERLEAVED
CL = 2.5
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
f
f
f
f
0-1
1-0
167
133
133
133
256MB, 512MB, 1GB, 2GB (x72, ECC, DR)
9
Operating Mode
MODE REGISTER SET command with bits A7–A11
(256MB); A7–A12 (512MB, 1GB); or A7–A13 (2GB) each
set to zero, and bits A0–A6 set to the desired values. A
DLL reset is initiated by issuing a MODE REGISTER
SET command with bits A7 and A9–A11 (256MB); A7
and A9–A12 (512MB, 1GB); or A7 and A9–A13 (2GB)
each set to zero, bit A8 set to one, and bits A0–A6 set to
the desired values.
Micron device, JEDEC specifications recommend
when a LOAD MODE REGISTER command is issued to
reset the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.
(256MB); A7–A12 (512MB, 1GB); or A7–A13 (2GB) are
reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.
Extended Mode Register
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram, on page 10. The extended mode
COMMAND
COMMAND
The normal operating mode is selected by issuing a
All other combinations of values for A7–A11
The extended mode register controls functions
DQS
DQS
CK#
CK#
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
CK
CK
184-PIN DDR SDRAM UDIMM
READ
READ
Burst Length = 4 in the cases shown
Shown with nominal t AC, t DQSCK, and t DQSQ
T0
T0
CL = 2
TRANSITIONING DATA
Although not required by the
CL = 2.5
NOP
NOP
T1
T1
©2004 Micron Technology, Inc. All rights reserved.
T2
NOP
NOP
T2
T2n
T2n
DON’T CARE
T3
NOP
NOP
T3
T3n
T3n