mt18vddt12872ag-335 Micron Semiconductor Products, mt18vddt12872ag-335 Datasheet - Page 11

• Manufacturer Part Number: mt18vddt12872ag-335
• Description: 256mb, 512mb, 1gb, 2gb X72, Ecc, Dr 184-pin Ddr Sdram Udimm
• Manufacturer: Micron Semiconductor Products

Commands
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
Table 8:
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
Table 9:
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef80814e61, source: 09005aef807f8acb
DD18C32_64_128_256x72AG.fm - Rev. B 9/04 EN
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (256MB); or A0–A12 (512MB, 1GB); A0–A13 (2GB) provide row
3. BA0–BA1 provide device bank address; A0–A9 (256MB, 512MB) or A0–A9, A11(1GB, 2GB), provide column address; A10
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
Table 8, Commands Truth Table, and Table 9, DM
address.
HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are “Don’t Care.”
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (256MB); A0–A12
(512MB, 1GB); or A0–A13 (2GB) provide the op-code to be written to the selected mode register.
Commands Truth Table
DM Operation Truth Table
256MB, 512MB, 1GB, 2GB (x72, ECC, DR)
11
CS#
H
of commands and operations, refer to the 128Mb,
256Mb, 512Mb, or 1Gb DDR SDRAM component data
sheet.
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
RAS#
X
H
H
H
H
L
L
L
L
CAS#
X
H
H
H
H
L
L
L
L
WE#
H
H
H
H
X
L
L
L
L
©2004 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
X
X
X
X
DM
H
L
NOTES
6, 7
1
1
2
3
3
4
5
8
Valid
DQS
X